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S5D4100X
Data Sheet
Revision 0.1
RECORD OF REVISIONS
Rev. No 0.0 0.1 Date 2004/12 2005/3 12 ~ 14 12 Page First Release Output drive current and Pull Up/Down Pad descriptions Revision Point: PCKO output drive Current change (20mA 4mA) Description of Change
Table of Contents
1. overview ..................................................................................................................................................7 1.1 Features ............................................................................................................................................8 2. pin CONFIGURATIONS ..........................................................................................................................9 2.1 Pin Descriptions ..............................................................................................................................12 3. Functional Block Diagram .....................................................................................................................15 4. Solution Circuit for Application ..............................................................................................................16 5. functional description.............................................................................................................................18 5.1 Clock systems.................................................................................................................................18 5.2 ITU Decoder....................................................................................................................................19 5.3 BOOST-UP .....................................................................................................................................20 5.4 Sharpness, HUE & SAT..................................................................................................................21 5.5 Input Formatter & Test Pat. Gen.....................................................................................................22 5.6 BT656 Encoder ...............................................................................................................................24 5.7 Timing Generator ............................................................................................................................25 5.8 SCALER..........................................................................................................................................27 5.9 OSD (ON-Screen Display) ..............................................................................................................27 5.10 Contrast Control............................................................................................................................40 5.11 Gamma .........................................................................................................................................40 5.12 Host Interface................................................................................................................................41 5.13 Data output Formatter & Serial Interface ......................................................................................47 5.14 Power Down Control .....................................................................................................................50 6. Register Map .........................................................................................................................................51 6.1 GLOBAL..........................................................................................................................................51 6.2 Timing Generator ............................................................................................................................59 6.3 YC Processor..................................................................................................................................64 6.4 Scaler ..............................................................................................................................................71 6.5 Contrast...........................................................................................................................................73 6.6 Gamma ...........................................................................................................................................75 6.7 OSD ................................................................................................................................................78 6.8 BOOSTUP.......................................................................................................................................85
Table of Contents (Continued)
7. Electrical Specification.......................................................................................................................... 89 7.1 Absolute Maximum Ratings ........................................................................................................... 89 7.2 Recommended Operation Conditions............................................................................................ 89 7.3 DC Electrical Characteristics.......................................................................................................... 90 7.4 AC Electrical Characteristics.......................................................................................................... 91 8. Package Dimension.............................................................................................................................. 93 8.1 88-FBGA-0707 .............................................................................................................................. 93 8.2 80-TQFP-1212 .............................................................................................................................. 94
Figure of Contents
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 80-TQFP-1212 ..............................................................................................................9 88-FBGA-0707 (PAD Domain) ...................................................................................10 88-FBGA-0707............................................................................................................12 Functional Block Diagram...........................................................................................15 Solution Circuit for Application (TQFP).......................................................................16 Solution Circuit for Application (FBGA).......................................................................17 Clock Systems ...........................................................................................................18 ITU Decoder ...............................................................................................................19 Adaptive Brightness Control LUT ...............................................................................20 Sharpness I/O Characteristic Curve ...........................................................................21 Test Sync ...................................................................................................................22 TP_SEL Register ........................................................................................................22 Types of Pattern..........................................................................................................23 Pattern 6 (Constant Level) ..........................................................................................23 Input Timing ................................................................................................................25 Structure of Frequency Synthesized PLL ...................................................................26 OSD Font Structure ....................................................................................................27 OSD DISPLAY RAM Structure ...................................................................................28 OSD Position .............................................................................................................29 Board/Shadow ...........................................................................................................30 Creating Border When There is No Space on the Right ............................................31 When There is no Space on the Left ..........................................................................32 Creating Border on the Left Space .............................................................................32 OSD Multicolor Font Structure....................................................................................34 OSD Region Definition................................................................................................35 OSD RAM Structure....................................................................................................36 OSD Font Structure ....................................................................................................37 OSD Font RAM & Display RAM Structure ..................................................................38 OSD System Block Diagram.......................................................................................39 Gamma Graph ...........................................................................................................40 6-wire Host Interface Write Data Sequence (Sending n data) ...................................41 6-wire Host Interface Read Data Sequence (Reading n data) ...................................42 I2C Host Interface Write Data Sequence ...................................................................43 I2C Host Interface Read Data Sequence ...................................................................43 3-wire Host Interface Write Data Sequence ...............................................................45 3-wire Host Interface Read Data Sequence ...............................................................45 PWM ...........................................................................................................................46 Parallel interface Panel Architecture...........................................................................47 Parallel Output Data....................................................................................................47 Delta Type Panel Architecture ....................................................................................48 Serial Output Data ......................................................................................................48
DATASHEET
S5D4100X
1. OVERVIEW
S5D4100X is a digital interface including Scaler, Image Enhancement, ITU-R VT656 Decoder, OSD, GAMMA and DITHER. S5D4100X supports two ITU-R BT656 Video inputs or one ITU-R BT601 input, and provides R/G/B Serial and ITU-R 656 Outputs or R/G/B Parallel Output
7
DATASHEET
S5D4100X
1.1 FEATURES Input Format - - ITU-R BT601 / ITU-R BT656 Video Format Support Dual ITU-R BT656 Channel Port
ITU Decoder - - ITU-R BT656 Decoding Support NTSC / PAL System
Image Enhancement - - - Image Boost-Up (Adaptive Contrast Control) Sharpness Control Color Hue & Saturation Control
High-Quality Advanced Scaling - - Fully Programmable Image Scaling (Up to XGA) Independent Horizontal / Vertical Image Scale-Up and / or Scale-Down
Built-in On-Screen Display - - - Programmable Character RAM Fonts (256 Fonts) User Friendly Font Size (12x18) and Display Font Number of Window Frame (Up to 450) Various Font Attribute (Raster Enable, Blink, Character Border/Shadow Enable, Half-Tone, Intensity)
Economic Clock Source - - External X-tal Application (Optional) Programmable Frequency Synthesize in Built-in PLL Core
Supports I2C Bus & 3-Wired / 6-Wired Serial Host Interface R/G/B Gamma look-up table 8 to 6 bit Dithering Built-in RGB Black Level / Bright / Contrast Control Application based Output Data Interface - - - - R/G/B Serial Output for RGB-Dot-Pixel LCD Panel R/G/B Parallel Output for RGB-Pixel Panel ITU-R656, 8-Bit 4:2:2 Data with Embedded Sync Output for External Application
Fab. & PKG Information - - Fab. Process: L18 (0.18 m) PKG: 88-FBGA-0707 / 80-TQFP-1212
Operating Conditions - 1.8 Volts Internal Core Logic, 3.3 Volts I/O Driver Power
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DATASHEET
S5D4100X
2. PIN CONFIGURATIONS
YI7 YI6 YI5 YI4 YI3 VDDP VSSP YI2 YI1 YI0 CI7 CI6 CI5 VDDC VSSC CI4 CI3 CI2 CI1 CI0
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VCKI TEST PWM1 PWM0 VSSC VDDC SDA3 SDA2 SDA1 SDA0 SCL SCSN RSTN HIF VSSP VDDP BO7 BO6 BO5 BO4
S5D4100X
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
BO3 BO2 BO1 BO0 VSSC VDDC GO7 GO6 GO5 GO4 GO3 GO2 GO1 GO0 VSSP VDDP RO7 RO6 RO5 RO4
HD VD FLD XI XO VDDP VSSP FILT VDDAP VSSAP PVSO PHSO PDEO PCKO VDDC VSSC RO0 RO1 RO2 RO3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Figure 1. 80-TQFP-1212
9
DATASHEET
S5D4100X
NC YI7 YI6 YI5 YI4 YI3 VDDP VSSP YI2 YI1 YI0 CI7 CI6 CI5 VDDC VSSC CI4 CI3 CI2 CI1 CI0 NC
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
NC VCKI TEST PWM1 PWM0 VSSC VDDC SDA3 SDA2 SDA1 SDA0 SCL SCSN RSTN HIF VSSP VDDP BO7 BO6 BO5 BO4 TD0
S5D4100X
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
TDI BO3 BO2 BO1 BO0 VSSC VDDC GO7 GO6 GO5 GO4 GO3 GO2 GO1 GO0 VSSP VDDP RO7 RO6 RO5 RO4 TRST
10
TMS HD VD FLD XI XO VDDP VSSP FILT VDDAP VSSAP PVSO PHSO PDEO PCKO VDDC VSSC RO0 RO1 RO2 RO3 TCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Figure 2. 88-FBGA-0707 (PAD Domain)
DATASHEET
S5D4100X
88-FBGA-0707
N M L K J H G F E D C B A
O O O O O O O O O O O O O
O O O O O O O O O O O O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O O O O O O O O O O
O O O O O O O O O O O O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
1
2
3
4
5
6
7
8
9
10 11 12 13
Figure 3. 88-FBGA-0707
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DATASHEET
S5D4100X
2.1 PIN DESCRIPTIONS
Terminal Number Name TQFP TMS HD VD FLD XI XO VDDP VSSP FILT VDDAP VSSAP PVSO PHSO PDEO PCKO VDDC VSSC RO0 RO1 RO2 RO3 TCK TRST RO4 RO5 RO6 RO7 VDDP VSSP GO0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FBGA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 K1 K2 L1 L2 M1 M2 N1 N2 M3 N3 M4 N4 M5 N5 I I I I I O P G O P G O O O O P G O O O O I I O O O O P G O I/O Output drive current 12.1mA 0.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA Pull up down up down up -
Description
JTAC mode (Boundary Scan Design) Horizontal Driving Pulse in ITU-R. BT601 /VCKI_B in ITUR. BT656 Vertical Driving Pulse in ITU-R. BT601 / VSYNC_A in ITUR. BT656 Field Identification in ITU-R. BT601 /VSYNC_B in ITU-R. BT656 X-tal Input for External Clock Reference (Free-Run Clock) X-tal Output for External Clock Reference I/O Pad Drive VDD (3.3V) I/O Pad Drive VSS External Loop Filter Terminal for Built-In PLL Analog VDD for Built-in PLL (1.8V) Analog VSS for Built-in PLL Vertical Sync Output for LCD Panel Horizontal Sync Output for LCD Panel Data Enable Output for LCD Panel System Clock Output for LCD Panel Internal Core Drive VDD (1.8V) Internal Core Drive VSS R-CH Output 0 / Serial Output 0 [LSB] R-CH Output 1 / Serial Output 1 R-CH Output 2 / Serial Output 2 R-CH Output 3 / Serial Output 3 JTAC mode (Boundary Scan Design) JTAC mode (Boundary Scan Design) R-CH Output 4 / Serial Output 4 R-CH Output 5 / Serial Output 5 R-CH Output 6 / Serial Output 6 R-CH Output 7 / Serial Output 7 [MSB] I/O Pad Drive VDD (3.3V) I/O Pad Drive VSS G-CH Output 0 / General Purpose Output 0
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DATASHEET
S5D4100X
Terminal Name TQFP GO1 GO2 GO3 GO4 GO5 GO6 GO7 VDDC VSSC BO0 BO1 BO2 BO3 TDI TDO BO4 BO5 BO6 BO7 VDDP VSSP HIF RSTN SCSN SCL SDA0 SDA1 SDA2 SDA3 VDDC 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Number FBGA 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 M6 N6 M7 N7 M8 N8 M9 N9 M10 N10 M11 N11 N13 N12 M13 M12 L13 L12 K13 K12 J13 J12 H13 H12 G13 G12 F13 F12 E13 E12 O O O O O O O P G O O O O I O O O O O P G I I I I I/O I/O I/O I/O P I/O
Output drive current 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA 4.0mA -
Pull up down up down -
Description
G-CH Output 1 / General Purpose Output 1 G-CH Output 2 / General Purpose Output 2 G-CH Output 3 / General Purpose Output 3 G-CH Output 4 / General Purpose Output 4 G-CH Output 5 / General Purpose Output 5 G-CH Output 6 / ITU-R656 VSYNC Output for NonStandard Sync Mode G-CH Output 7 / ITU-R656 VCK Output Internal Core Drive VDD (1.8V) Internal Core Drive VSS B-CH Output 0 / ITU-R656 Output 0 [LSB] B-CH Output 1 / ITU-R656 Output 1 B-CH Output 2 / ITU-R656 Output 2 B-CH Output 3 / ITU-R656 Output 3 JTAC mode (Boundary Scan Design) JTAC mode (Boundary Scan Design) B-CH Output 4 / ITU-R656 Output 4 B-CH Output 5 / ITU-R656 Output 5 B-CH Output 6 / ITU-R656 Output 6 B-CH Output 7 / ITU-R656 Output 7 [MSB] I/O Pad Drive VDD (3.3V) I/O Pad Drive VSS Host Interface Select ("0":3-Wired or 6-Wired, "1": IIC) System Reset Chip Select of the Host Interface Clock of the Host Interface Data/Address 0 of the Host I/F [LSB] / SDA in case of IIC Data/Address 1 of the Host I/F Data/Address 2 of the Host I/F Data/Address 3 of the Host I/F [MSB] Internal Core Drive VDD (1.8V)
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DATASHEET
S5D4100X
Terminal Name TQFP VSSC PWM0 PWM1 TEST VCKI NC NC YI7 YI6 YI5 YI4 YI3 VDDP VSSP YI2 YI1 YI0 CI7 CI6 CI5 VDDC VSSC CI4 CI3 CI2 CI1 CI0 NC 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Number FBGA 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 D13 D12 C13 C12 B13 A13 B12 A12 B11 A11 B10 A10 B9 A9 B8 A8 B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 A1 A2 I I I I I P G I I I I I I P G I I I I I G O O I I I/O
Output drive current 4.0mA 4.0mA -
Pull up down down down down down
Description
Internal Core Drive VSS Pulse Width Modulation 0 Pulse Width Modulation 1 Test Input (Pull-Down) Video Clock Input in ITU-R. BT601 / VCKI_A in ITU-R. BT656 No Connect No Connect Luminance Data Input 7 / ITU-R656 Data A Input 7 [MSB] Luminance Data Input 6 / ITU-R656 Data A Input 6 Luminance Data Input 5 / ITU-R656 Data A Input 5 Luminance Data Input 4 / ITU-R656 Data A Input 4 Luminance Data Input 3 / ITU-R656 Data A Input 3 I/O Pad Drive VDD (3.3V) I/O Pad Drive VSS Luminance Data Input 3 / ITU-R656 Data A Input 2 Luminance Data Input 3 / ITU-R656 Data A Input 1 Luminance Data Input 3 / ITU-R656 Data A Input 0 [LSB] Chrominance Data Input 7 / ITU-R656 Data B Input 7 [MSB] Chrominance Data Input 6 / ITU-R656 Data B Input 6 Chrominance Data Input 5 / ITU-R656 Data B Input 5 Internal Core Drive VDD (1.8V) Internal Core Drive VSS Chrominance Data Input 4 / ITU-R656 Data B Input 4 Chrominance Data Input 3 / ITU-R656 Data B Input 3 Chrominance Data Input 2 / ITU-R656 Data B Input 2 Chrominance Data Input 1 / ITU-R656 Data B Input 1 Chrominance Data Input 0 / ITU-R656 Data B Input 0 [LSB] No Connect
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DATASHEET
S5D4100X
3. FUNCTIONAL BLOCK DIAGRAM
YI7~YI0 CI7~CI0 HD VD FLD
ITU-R BT601/656 ITU Decoder BOOSTUP
Y Cr/Cb
Sharpness, HUE & SAT
YCbCr to RGB
Input Formatter & Test Pat. Gen.
PWM & GPO GEN. PWM0 PWM1
GPO Front OSD
RGB to OSD MIX YCbCr
BT656 Encoder
OSD SFC RAM FONT Post OSD 8 to 6-bit Dither Scaling Engine Contrast Gamma Correction
Output Data Formatter
RO7~RO0 GO7~GO0 BO7~BO0
PHSO PVSO PDEO PCKO
VCKI XI
CKI Timing Generator PLL CKOSC Int.OSC CKO Hardware Reset Sync Delay Match Host Interface
XO
FILT
RSTN
HIF SCSN SCL SDA0~3
Figure 4. Functional Block Diagram
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DATASHEET
S5D4100X
4. SOLUTION CIRCUIT FOR APPLICATION
VIDEO_INPUT_CK
PWM1 PWM0
SDA3 SDA2 SDA1 SDA0 SCL SCSN RSTN
4100_+3.3VD 4.7 4.7 4.7 4.7 4.7 4.7 4.7
4100_+1.8VD
SW
IIC 3or6 Wired
1 2 3
1 2 3
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VIDEO_INPUT_Y7 VIDEO_INPUT_Y6 VIDEO_INPUT_Y5 VIDEO_INPUT_Y4 VIDEO_INPUT_Y3 VIDEO_INPUT_Y2 VIDEO_INPUT_Y1 VIDEO_INPUT_Y0 VIDEO_INPUT_C7 VIDEO_INPUT_C6 VIDEO_INPUT_C5 VIDEO_INPUT_C4 VIDEO_INPUT_C3 VIDEO_INPUT_C2 VIDEO_INPUT_C1 VIDEO_INPUT_C0
4100_+1.8VP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
HD VD FLD XI XO VDDP DSSP FILT VDDAP VSSAP PVSO PHSO PDEO PCKO VDDC VSSC RO0 RO1 RO2 RO3
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
YI7 YI6 YI5 YI4 YI3 VDDP VSSP YI2 YI1 YI0 CI7 CI6 CI5 DVVC VSSC CI4 CI3 CI2 CI1 CI0
S5D4100X 80-TQFP-1212
BO3 BO2 BO1 BO0 VSSC VDDC GO7 GO6 GO5 GO4 GO3 GO2 GO1 GO0 VSSP VDDP RO7 RO6 RO5 RO4
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
B_CH_OUTPUT7 B_CH_OUTPUT6 B_CH_OUTPUT5 B_CH_OUTPUT4 B_CH_OUTPUT3 B_CH_OUTPUT2 B_CH_OUTPUT1 B_CH_OUTPUT0 G_CH_OUTPUT7 G_CH_OUTPUT6 G_CH_OUTPUT5 G_CH_OUTPUT4 G_CH_OUTPUT3 G_CH_OUTPUT2 G_CH_OUTPUT1 G_CH_OUTPUT0 R_CH_OUTPUT7 R_CH_OUTPUT6 R_CH_OUTPUT5 R_CH_OUTPUT4 R_CH_OUTPUT3 R_CH_OUTPUT2 R_CH_OUTPUT1 R_CH_OUTPUT0 OUTPUT_CK OUTPUT_DE OUTPUT_HS OUTPUT_VS
VIDEO_INPUT_HS VIDEO_INPUT_VS VIDEO_INPUT_FLD 1
25MHz D_GND 22pF 22pF 5.1nF 68nF
Figure 5. Solution Circuit for Application (TQFP)
16
VCKI TEST PWM1 PWM0 VSSC VDDC SDA3 SDA2 SDA1 SDA0 SCL SCSN RSTN HIF VSSP VDDP BO7 BO6 BO5 BO4 3.3 D_GND
DATASHEET
S5D4100X
VIDEO_INPUT_CK
PWM1 PWM0
SDA3 SDA2 SDA1 SDA0 SCL SCSN RSTN
4100_+3.3VD 4.7 4.7 4.7 4.7 4.7 4.7 4.7
4100_+1.8VD
SW
IIC 3or6 Wired
1 2 3
1 2 3
A13 B13 C12 C13 D12 D13 E12 E13 F12 F13 G12 G13 H12 H13 J12 J13 K12 K13 L12 L13 M12 M13
VIDEO_INPUT_Y7 VIDEO_INPUT_Y6 VIDEO_INPUT_Y5 VIDEO_INPUT_Y4 VIDEO_INPUT_Y3 VIDEO_INPUT_Y2 VIDEO_INPUT_Y1 VIDEO_INPUT_Y0 VIDEO_INPUT_C7 VIDEO_INPUT_C6 VIDEO_INPUT_C5 VIDEO_INPUT_C4 VIDEO_INPUT_C3 VIDEO_INPUT_C2 VIDEO_INPUT_C1 VIDEO_INPUT_C0
B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 K1 K2 L1 L2 M1 M2
4100_+1.8VP
TMS HD VD FLD XI XO VDDP VSSP FILT VDDAP VSSAP PVSO PHSO PDEO PCKO VDDC VSSC RO0 RO1 RO2 RO3 TCK
B12 A12 B11 A11 B10 A10 B9 A9 B8 A8 B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 A1 A2
NC YI7 YI6 YI5 YI4 YI3 VDDP VSSP YI2 YI1 YI0 CI7 CI6 CI5 VDDC VSSC CI4 CI3 CI2 CI1 CI0 NC
S5D4100X 88-FBGA-0707
TDI BO3 BO2 BO1 BO0 VSSC VDDC GO7 GO6 GO5 GO4 GO3 GO2 GO1 GO0 VSSP VDDP RO7 RO6 RO5 RO4 TRST
N12 N13 N11 M11 N10 M10 N9 M9 N8 M8 N7 M7 N6 M6 N5 M5 4N M4 N3 M3 N2 N1
B_CH_OUTPUT7 B_CH_OUTPUT6 B_CH_OUTPUT5 B_CH_OUTPUT4 B_CH_OUTPUT3 B_CH_OUTPUT2 B_CH_OUTPUT1 B_CH_OUTPUT0 G_CH_OUTPUT7 G_CH_OUTPUT6 G_CH_OUTPUT5 G_CH_OUTPUT4 G_CH_OUTPUT3 G_CH_OUTPUT2 G_CH_OUTPUT1 G_CH_OUTPUT0 R_CH_OUTPUT7 R_CH_OUTPUT6 R_CH_OUTPUT5 R_CH_OUTPUT4 R_CH_OUTPUT3 R_CH_OUTPUT2 R_CH_OUTPUT1 R_CH_OUTPUT0 OUTPUT_CK OUTPUT_DE OUTPUT_HS OUTPUT_VS
VIDEO_INPUT_HS VIDEO_INPUT_VS VIDEO_INPUT_FLD 1
25MHz D_GND 22pF 22pF 5.1nF 68nF
Figure 6. Solution Circuit for Application (FBGA)
NC VCKI TEST PWM1 PWM0 VSSC VDDC SDA3 SDA2 SDA1 SDA0 SCL SCSN RSTN HIF VSSP VDDP BO7 BO6 BO5 BO4 TDO 3.3 D_GND
17
DATASHEET
S5D4100X
5. FUNCTIONAL DESCRIPTION
5.1 CLOCK SYSTEMS Figure 7 shows the names of the clocks used in each block of S5D4100X and the registers that affect them. As illustrated in the following system diagram, each block is designed to enable the user to switch on/off clocks at his/her need. For example, in order to activate the scaler, the clock is supplied only when Register GBI_ON, SC_ON, and GBO_ON are HIGH. Register ENC_ON, Register BU_ON and Register OSD_ON should be HIGH to enable ITU-R656 format output, BOOST-UP function and OSD menu function, respectively. In this manner, the system is configured to minimize power consumption in the portable devices which are the main applications.
SCL XI VCK HD 0 1 0 1 CKOSC_SEL
SCL Host Interface CKOSC
ITU656_CH 0
2MUL 2DIV
ITU_CK GBI_ON ENC_CK ENC_ON 0 0 1 CKI_SEL V601 0 1 BU_CKI BU_ON GB_CKI GBI_ON OSD_CK OSD_ON
ITU Decoder
1
BT656 Ecoder
BOOSTUP
Sharpness, Hue&SAT
YCbCr to RGB
PLL_P PLL_M PLL_S
PLL [1:0] PLL_DIV [4:2] 0 1 CKO_SEL
1
FRONT_OSD Scaling Ck_Gen. SCALER_CK SC_ON
Input Formatter & Test Pat. Gen.
RGB to YCbCr
OSD
GB_CKO GBO_ON
SFC & Scaling Engine
: Intenal Node or Register : I/O Port : Functional Block
Contrast
Gamma
Dither
Output Data Formatter
Figure 7. Clock Systems
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DATASHEET
S5D4100X
5.2 ITU DECODER The ITU decoder block divides Y, C and sync signal from the BT656 data via decoding of the input data in accordance with the protocol. For BT656 input image, the ITU decoder block selects two channels alternatively. If the value of Register ITU656_CH is LOW, pins YI7 ~ YI0 are used for BT656 data, VCKI for input clock, and VD for input vertical sync signal. On the contrary, if the value of Register ITU656_CH is HIGH, pins CI7 ~ CI0 are used for BT656 data, HD for input clock, and FLD for input vertical sync signal. In other words, for ITU-R BT656, two input sources are used selectively for image by alternating channels. For ITU-R BT601 input, the ITU decoder block simply multiplexes the data and the sync signal.
FLD
10
FLDi
HD 10 VD
HDi
10
VDi
10 YI7~0 0 1 CI7~0 ITU656_CH V601 Y+C 656 Decoder C656 0 1 Y656
Yi
Ci
Figure 8. ITU Decoder
19
DATASHEET
S5D4100X
5.3 BOOST-UP The BOOST-UP block performs image enhancement so that the image can be seen more clearly. Main functions of image boost-up are as follows. 5.3.1 Adaptive Contrast Control This function makes a certain area or the entire area of the screen clearer. This is achieved as the block sorts out the colors being displayed on the screen, finds the maximum and the minimum value, and displays the image with the colors calculated adaptively through the contrast control processing. 5.3.2 Adaptive Brightness Control This function makes the screen brighter in accordance with the LUT value. As shown in Figure 9, LUT is a value between 0 ~ 255, and maps input/output in 1:1 ratio. The size of the curve A configured in accordance with input/output mapping varies adaptively in accordance with the brightness of the screen. Point B is the inflection point of the curve which should be set by the turning point Register (TURN_POINT). All the values of LUT should be set to the size of the absolute value. The values in the area lower than Register TURN_POINT (Area C) are automatically calculated as the negative values. 5.3.3 Boost Up Calculation Area The Boost-Up block reflects the previous screen status in the current screen. The area in which the screen status is judged becomes the calculation area. The screen is divided into the calculation area and the reflected area in order to prevent the screen from being affected by other data such as caption dialog than the actual video image.
O 255 A
C
B
0
255
I
Figure 9. Adaptive Brightness Control LUT
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DATASHEET
S5D4100X
5.4 SHARPNESS, HUE & SAT 5.4.1 Sharpness
CORE_L*2
CORE_H*2
EDGE_LIM
0
- EDGE_LIM
- CORE_H*2
- CORE_L*2
Figure 10. Sharpness I/O Characteristic Curve The Sharpness block applies "0" for any value smaller than two times of Register CORE_L shown in Figure 10, applies a certain gradient for the value smaller than two times of Register CORE_H, and bypasses edge value for the area bigger than two times of Register Core_H. Any value which is bigger than Register EDGE_LIM is limited to Register EDGE_LIM. The gradient between Register CORE_L and Register CORE_H is determined by Register CORE_RATE; 1/2, 1/4, 1/8 and 1/16 for 00, 01, 10 and 11, respectively. BLACK/BRIGHTNESS/CONTRAST can be adjusted as following, after EDGE is reflected. YOUT = (YIN - YCP_BLACK) * YCP_CONTRAST + YCP_BRIGHTNESS Where, Register YCP_BRIGHTNESS is a 2's complement, and can be a negative number. 5.4.2 HUE & SAT Register HUE can be adjusted between -180 degree and +180 degree. The value can be a 2's complement between -512 and +511. Register SATURATION is applied after adjustment of Register HUE.
21
DATASHEET
S5D4100X
5.5 INPUT FORMATTER & TEST PAT. GEN. 5.5.1 Input Formatter The Input Formatter block transforms the input data into the format appropriate for SFC. The block generates input sync, and adjusts Vsync delay of the odd/even field. 5.5.2 Test Pat. Gen. The Test Pat. Gen. block generates a pattern for sync and test without input sync and data, and uses it as the input for SFC. In order to use the test data of the Test Pat. Gen. block, Register TEST_PAT_ON should be HIGH. In order to use the test sync, Register TP_SYNC_ON should be HIGH. Figure 11 shows the internally generated sync.
20 HS
30
Active Data Area
10
3 VS
16
Active Line Area
1
Figure 11. Test Sync The active data area and the active line area are as specified in Registers HIAS and VIAS. The pattern to be used as the input data for SFC is selected by Register TP_SEL. The image is passed if Bit [7] is 0, and inverted if it is 1. Bit [5] is used to select direction (H/V) of the pattern. Bits [4] ~ [0] are used to select type of the pattern. The following figure summarizes the above description.
[7] [6] [5] [4] [3] [2] [1] [0] X INV. 0~9 : Type of Pattern H/V SEL not USE
Figure 12. TP_SEL Register
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Types of pattern selected by Bits [4] ~ [0] are as follows.
0
1
2
3
4
Constant Level
5
6
7
8
9
Figure 13. Types of Pattern Pattern No 6, Constant level in the above figure is decided depending on the Register TP_CONST_LEVEL and TP_CONST_WIDTH. If Register TP_CONST_WIDTH is 0, the value set in Register TP_CONST_LEVEL is displayed. If Register TP_CONST_WIDTH is other than 0, starting at the value set in Register TP_CONST_LEVEL, the number of pixels in Register TP_CONST_WIDTH is counted from left to right in the screen, and then, at the TP_CONST_LEVEL +1, the pixels set in Register TP_CONST_WIDTH is displayed. In other words, the screen is displayed as shown in the following figure.
TP_CONST_WIDTH TP_CONST_LEVEL+1 TP_CONST_LEVEL+2
Figure 14. Pattern 6 (Constant Level)
TP_CONST_LEVEL
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In case of other registers related to the Test Pat. Gen. block, if Register TP_YUV_ON is HIGH, the display of the Test Pat. Gen. block is sent to the BOOST-UP block. This is the flow to test the BOOST-UP block, and is not used in general screen test. Register TP_RGB_ON consists of R, G and B by 2 bits from front (Y, Cb and Cr if Register TP_YUV_ON is HIGH). The following table shows the display ratio. Table 1. Test Pattern Display Ratio R/G/B Display ratio 00 0% 01 25% 10 50% 11 100%
5.6 BT656 ENCODER The BT656 encoder outputs the ITU-R656 data via the pins BO0 ~ BO7 when Register SERIAL_ON and Register ENC_ON are HIGH. The encoder also outputs VCKO and VSO via GO7 and GO6. The outputs of the BT656 encoder are determined in accordance with the Register EN_656OUTSEL values as shown in the following table. Table 2. Encoder Output EN_6565OUTSEL 00 01 10 11 Output Input 656 data (The channel selected in accordance with Register ITU656_CH value) ITU decoder output data (If Register VS_SEL is HIGH, the 656 data contains VS instead of VACT) Sharpness, HUE & SAT output data OSD output data if FRONT_OSD is HIGH, and input formatter output data if it is LOW.
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5.7 TIMING GENERATOR The timing generator generates the timing used in S5D4100X, and delivers the value required for PCKO (output clock). Using input HS and VS, the timing generator generates PHSO, PVSO and PDEO for output sync. The generated timing signals are sent to the internal blocks. TG also delivers the value for generation of PCKO from MCU to internal PLL. 5.7.1 Output Timing Generation Using input HS and VS, TG generates the output sync (PHSO, PVSO and PDEN). To set the active data area in input HS and VS, values for Register HTOTAL, H_STR, HIAS, VTOTAL, V_STR and VIAS are set as shown in Figure 15. The output signals are defined with the values of Register HOFP, HOSW, HOBP, VOFP, VOSW, HOAS and VOAS.
HTOTAL HSW Horizontal Sync Input H_STR HIAS HBP H_Active Data_Area HFP
VTOTAL VSW Vertical Sync Input V_STR VIAS VBP V_Active Data_Area VFP
Figure 15. Input Timing
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5.7.2 Output Clock Generation S5D4100X generates output clock with PLL. Figure 16 shows the structure of PLL. Receiving the input clock Fin from VCK or X1 pin, the Pre-Divider divides the clock, using the Register PLL_P value, and send them to PFD. PFD uses the signal received from the Pre-Divider as the reference frequency, compares the signal with the output of the main divider which is determined by the Register PLL_M value, and controls the charge pump voltage. VCO generates the output clock, and supplies the final output clock (FOUT) via Post Scaler1 and Post Scaler2. The signal is divided for lower 2 bits of Register PLL_S for Post Scaler1, and upper 3 bits of Register PLL_S for Post Scaler2. The frequency of FOUT is calculated as: FOUT = Fin * (Pll_M+1) / (PLL_P * 2S) Where, S = PLL_S[4:2] + PLL_S[1:0].
HS Charge Pump Post Scaler 1 2 PLL_P Main Divider PLL_S[1:0] Post Scaler 2 3 PLL_S[4:2]
Fin
Pre-Divider
PFD
VCO
FOUT
PLL_M
Figure 16. Structure of Frequency Synthesized PLL
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5.8 SCALER The scaler of S5D4100X runs in the following 4 image scaling modes. (1:1 mode is Scale Up.) 5.8.1 HUPVUP (Horizontal-Scale-Up, Vertical-Scale-Up) For ITU-R.656/601 input, the scaler guarantees clock speed of 80MHz to XGA output. The scaler supports scaleup of up to 1024 pixels in horizontal direction, and up to 768 lines in vertical direction. The scaler supports scaleup at different ratio in H/V direction respectively. 5.8.2 HDNVDN (Horizontal-Scale-Down, Vertical-Scale-Down) For ITU-R.656/601 input, the scaler supports scale-down to 1/2 size. For NT input, the scaler supports scaledown of up to 360 pixels in the horizontal direction, and up to 120 lines in the vertical direction. The scaler supports scale-up at different ratio in H/V direction respectively. 5.8.3 HUPVDN (Horizontal-Scale-Up, Vertical-Scale-Down) For ITU-R.656/601 input, the scaler supports scale-up of up to 1024 pixels in the horizontal direction, and scaledown of up to 1/2 in the vertical direction. For NT input, the scaler supports scale-up of up to 1024 pixels in the horizontal direction and scale-down of up to 120 lines in the vertical direction. 5.8.4 HDNVUP (Horizontal-Scale-Down, Vertical-Scale-Up) For ITU-R.656/601 input, the scaler supports scale-down of up to 1/2 in the horizontal direction, and scale-up of up to 768 lines in the vertical direction. For NT input, the scaler supports scale-down of up to 360 pixels in the horizontal direction, and scale-up of up to 768 lines in the vertical direction.
5.9 OSD (ON-SCREEN DISPLAY) OSD stores the Font RAM address and the font features in the Display RAM, displays the font and its features in the designated location, and displays the features designated in OSD register on the screen. 5.9.1 FONT
12 Raster
18
A
Font
Character
Figure 17. OSD Font Structure OSD font is configured with 12*18 (W*L) pixels, and is divided into character and raster when displayed on the screen. Font color can be controlled with FC of Display RAM, and a font has 16 kinds of character color and 16 kinds of raster colors. FC value is used as the reference of LUT for controlling of character and raster.
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5.9.2 LUT (Look Up Table) Control The user can assign a bit to Register LUT0 ~ LUT15, and the color is displays in reference to the color elements of the values. For font color (Register FC), if Register FC == 3, LUT3 is assigned to the font, and hence, the character color has R= LUT3[7] , G= LUT3[6:5] and B= LUT3[4], and the raster color has R= LUT3[3], G= LUT3[2:1], B= LUT3[0]. For Character Border/Shadow Color (Register CH_BSC), R= LUTn[7] , G= LUTn[6:5] and B= LUTn[4] are assigned (n = 0 ~ 15). For MCF Color, R= LUTn[7], G= LUTn[6:5] and B= LUTn[4] are assigned (n = 0 ~ 7), and in this case, Register CH_BSC is available for LUT0 ~LUT7 only.
5.9.3 User Definable OSD Region OSD region is defined by the number of OSD horizontal fonts and the number of OSD vertical fonts to be displayed on the screen by Register OSD_HFONT[6:0] and Register OSD_VFONT[5:0]. Since 7 bits and 6 bits are assigned for Register OSD_HFONT and Register OSD_VFONT, respectively, the maximum fonts displayed are 127 in horizontal direction and 63 in vertical direction. Since the number of horizontal/vertical pixels of the minimum font is 12/18, the maximum pixels displayed in horizontal/vertical direction are 1524/1134 pixels. Because the maximum size of the display RAM is 450 * 2 (Display Ram attribute is 2 byte size), OSD_HFONT * OSD_VFONT <= 450 must be fulfilled. If Register OSD_HFONT is 30 and Register OSD_VFONT is 10, the OSD region is as in the following figure. In this case, the Display RAM uses addresses from 0x2000 to 0x2257 for display.
Display RAM Address 0x2000 & 0x2001 Display RAM Address 0x203E & 0x203F
12 1 2 3 4 5 6 7 8 9 10
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Figure 18. OSD DISPLAY RAM Structure
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5.9.4 OSD Position Start point of OSD can be changed via controlling of Register OSD_HSP and Register OSD_VSP.
Horizontal Active Area
(0,0) Vertical Active Area (OSD_HSP,OSD_VSP)
Figure 19. OSD Position 5.9.5 Adjustment of Font Size OSD font is stored on the Font RAM with 12 bits in a line, and is displayed in a 12*18 font via 18 accesses and displays in total. Horizontal/vertical size of a font can be enlarged to 1, 2, 3 and 4 times via adjustment of Register CH_HSZ and Register CH_VSZ. For example, 4 x Register CH_HSZ and 2 x OSD_VSZ will make the OSD font size 48*36. In this case, for 1 pixel of font data, the same data are displayed 4 times in horizontal direction and 2 times in vertical direction. Therefore, if Register CH_HSZ and Register CH_VSZ are changed, the OSD window size displayed on the screen is also changed.
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5.9.6 Character Border/Shadow The character border/shadow of a font is implemented as G_BDSH_EN of OSD Register is HIGH, Register CH_BDSH_EN of each character of Display RAM is HIGH, and Register BDSH_SEL is 1 or 0 (1: Border, 0: Shadow). If Register BDSH_TYPE_SEL (0x0108[7]) = 0, the size of border/shadow is decided in connection with the font size (Register CH_HSZ, Register CH_VSZ). For example, if Register CH_HSZ is 0, the character border/shadow is displayed by 1 pixel, and if Register CH_HSZ is 2, the character border/shadow is displayed in the thickness of 3 pixels. If Register BDSH_TYPE_SEL (0x0108[7]) = 1, regardless of the font size, the border/shadow is displayed in 1 pixel thickness. The border/shadow color of the character is decided by Register CH_BSC, and the value given in Register CH_BSC becomes the reference of LUT.
: Light Source
Figure 20. Board/Shadow
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S5D4100X
5.9.6.1 If there is no space on the right The border is created on the outside of the font area along the right side of the font. (This, however, is applied when Register BDSH_PASS (0x0108[6]) = 1. If Register BDSH_PASS = 0, the character border/shadow is created inside the font area.)
Font
Raster
Font
Font
Font Border The border is created on the raster area.
Font
Font
The border is not created on the font area.
Figure 21. Creating Border When There is No Space on the Right
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S5D4100X
5.9.6.2 If there is no space on the left No border shall be created on the left if there is no space on the left of the font.
Border is not created if the font area has no space.
Figure 22. When there is no Space on the Left In this case, the border can be created through modification of the font. (Shifting the entire font to the right by 1 pixel to create a space of 1 pixel on the left of the font)
1 Pixel space
Figure 23. Creating Border on the Left Space
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5.9.7 Blink Control OSD blink function can be controlled by font. The font blink function is enabled when Register BL_NTRA (Blink or NoTone Raster) is 1 and the Display RAM BLNK is 1 Register BLNK_SEL is used for adjustment of blink duty while the blink function is enabled. Table 3. Blink Control BLNK_SEL 0 1 2 3 4 5 6 7 Blink Off 0.5 sec 1 sec 0.5 sec 1 sec 1.5 sec 2 sec 1 sec 2 sec Blink On 0.5 sec 0.5 sec 1 sec 1 sec 1.5 sec 1 sec 2 sec 2 sec
Register BLNK_C supports color inversion of the character to be blinked. Once Register BLNK_C is set, the complementary color of the raster color of the current font is displayed on the character area during the blink off period, and if reset, the raster color is displayed.
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5.9.8 Multi-Colored Font (MCF) control OSD displays icons in multi-color. 8 (3-bit) or 4 (2-bit) multi-color fonts are available. Each multi-colored font consists of 3 colors attribute RAM fonts as shown in the following figure. The three fonts make a multi-colored font with the OR operation. Accessing a multi-colored font is performed via addressing of the first font. MCF starts from the point of font number 1 to the point in which Register N_MCF (0x0109[6:0]) becomes tripled (MCF_SEL = 0) or doubled (MCF_SEL = 1). If Register N_MCF is 4, font numbers 1 ~ 4 are R, 5 ~ 8 are G, and 9 ~ 12 are B-color fonts. The multi-colored font can be accessed via addressing of 1~4. For example, if Register N_MCF is 3, and the display RAM addresses 1, MCF uses 1 for the first font, 4 for the second font, and 7 for the third font. A pixel from each of the three fonts make a CHAR part via the OR operation. The three pixels are used as the selection [2:0] for Registers LUT1~LUT7. If the pixels are "000", the color of Register LUT0 is recognized as the raster, rather than the color of Register LUT0, and the attribute of the first font raster color is used. In other words, one of the 16 LUTs can be selected. If the G/B-color font is accessed instead of MCF R-color font, it is not recognized as MCF, but the Standard Font (SF) is used.
B B B B
1
1 0
LUT4 LUT6 LUT2
LUT7
LUT3
1 B
LUT1
4
7 Masked data of mulit-color font : Font Number 1 Displayed font : Font Number 1
Figure 24. OSD Multicolor Font Structure
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5.9.9 Blank Font Control If DSRAM font address attribute is 8'h00, 0x4000h of FTRAM is accessed and displayed, and only the input image is displayed in the OSD region. FTRAM 0x2000h is called as a blank font, and provides some useful function. For example, as the actual ODS window size is 30x10, the user can display this OSD window size as 20x5 by using blank fonts in the other area except 20x5.
Defined OSD region
Blank Font area
Actually displayed OSD region
Figure 25. OSD Region Definition
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5.9.10 OSD RAM
MICOM Interface
ADDR[13:0] ADDR[9:0] DATA[7:0] WEN
OSD
DISPLAY_RAM Control
DATA [15:0] ADDR DSRAM_ [8:0] WEN DATA [11:0]
Font_RAM Control
ADDR FTRAM_ [12:0] WEN
OSD Logic
DSRAM_ DOUT
Addr 0 1 2
Unused
INT or CH_BD CH_TP_ BLNK FC ADDR HT_EN SH_EN RA_EN INT or CH_BD CH_TP_ BLNK FC ADDR HT_EN SH_EN RA_EN
Addr 0 1 2
User Definable RAM FONT Data User Definable RAM FONT Data
FTRAM_DOUT
Display RAM
Font RAM
449 450
INT or CH_BD CH_TP_ BLNK FC ADDR HT_EN SH_EN RA_EN INT or CH_BD CH_TP_ BLNK FC ADDR HT_EN SH_EN RA_EN
4606 4607
User Definable RAM FONT Data User Definable RAM FONT Data 11 10 9 210
15
14
13
12
11~8 7~0
18*256 font
Figure 26. OSD RAM Structure The OSD RAM is divided into the font RAM and the display RAM. The font RAM stores 256 fonts of 12*18. The display RAM designates the font to be displayed on the screen, and the features including color.
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5.9.10.1 Font RAM Structure The font RAM has 9216 (4608*2) addresses from 0x4000 to 0x63FF, assigning 36 addresses per font (9216/256 = 36). Since the host interface transmits the data by 8 bits to the font RAM, in order to configure a font of 12*18 as shown in the following figure 27, an even numbered address and an odd numbered address are assigned to the upper 4 bits and the lower 8 bits of a line (12 bits), respectively.
To even numbered address To odd numbered address 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0x4024 0x4025 0x4026 0x4027 0x4028 0x4029 0x402A 0x402B 0x402C 0x402D 0x402E 0x402F 0x4030 0x4031 0x4032 0x4033 0x4034 0x4035 0x4036 0x4037 0x4038 0x4039 0x403A 0x403B 0x403C 0x403D 0x403E 0x403F 0x4040 0x4041 0x4042 0x4043 0x4044 0x4045 0x4046 0x4047 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX FONT RAM XXXX
Figure 27. OSD Font Structure
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5.9.10.2 Display RAM Structure The display RAM has 900 addresses from 0x2000 to 0x2383. In other words, 2 addresses are assigned to a display RAM cell (900/450 = 2). Since the host interface transmits the data by 8 bits, in order to configure a display RAM cell of 16 bits, 2 addresses should be transmitted. A display RAM cell is composed as below. In case of a display Ram cell [15] bit, the INTENSITY function or the HALF_TONE function is selected in accordance with Register DSRAM_ATTR_CON(0x010C[1]). The remaining one attribute is selected between Register G_INT(0x010C[0]) and Register G_HT_EN(0x010B[5]).
Font RAM 12 Font Number Display RAM 0x2000 Font Number 3 18 0 Font Number 2 Font Number 3 0x2001 0x2002 0x2003 0x2004 0x2005 0x2006 1 Font Number 0 Font Number 25 Font Number 44 2 Font Number 100 Font Number 68 3 Font Number 255 Font Number 210 ... Font Number 1 0x2007 0x2008 0x2009 0x200A 0x200B 0x200C 0x200D 0x200E 0x200F 0x2010 0x2011 0x2012 0x2013 ... 0x2382 0x2383
A B C
INT or HT
BDSH FC
BLINK TPRA
&
38
Even Address 255 Odd Address Font Number Display RAM Cell
Figure 28. OSD Font RAM & Display RAM Structure
DATASHEET
S5D4100X
MICOM INTERFACE
Data, Addr, Wen
OSD
Display Ram Control
RGB out Font Ram Control OSD Logic
Display Ram
Font Ram
Figure 29. OSD System Block Diagram
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5.10 CONTRAST CONTROL The contrast block is designed to control R/G/B of Register BLACK (0x0081~0x0083), Register CONTRAST (0x0084~0x0086) and Register BRIGHTNESS (0x0087~0x0089). The block can also control them individually based on R. Black level and Brightness play the role of offset, and Contrast plays the role of gain. Each pixel value is calculated as below. Rout = [Rin - Blacklevel(Red)] * Contrast(Red) + Brightness(Red) Gout = [Gin - Blacklevel(Green)] * Contrast(Green) + Brightness(Green) Bout = [Bin - Blacklevel(Blue)] * Contrast(Blue) + Brightness(Blue)
5.11 GAMMA The gamma correction block performs correction of the characteristics of the TFT-LCD panel. The block divides the input signal level into sections, generates the non-linear characteristic curve, and performs the gamma correction by substituting each section with linear function through linear interpolation. In other words, the block divides input into sections, and varies the output of each section to transform the characteristic curve for gamma correction. The input signal has the data level of 8 bits, and is equally divided into 32 sections with the interval of 8 between the sections. The block receives the output value for each equally divided level from MCU, performs non-linear gamma correction, and for the values between the levels, the block performs gamma correction via linear interpolation.
Y RYAV32 RYAV31 RYAV30
RYAV4 RYAV3 RYAV2 RYAV1
0
8
16
24
32
....
X 240 248 255
Figure 30. Gamma Graph
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5.12 HOST INTERFACE The host interface supports 3 protocols (6-Wire Host Interface Protocol, 3-Wire Host Interface Protocol and I2C Host Interface Protocol), and also supports the supplementary functions PWM and GPO. In order to use I2C Host Interface Protocol, HIF pin should be set to HIGH, and in order to use 3-Wire Host Interface Protocol, HIF pin should be set to LOW. To select 6-Wire Host Interface, as HIF = LOW, Register SIX_WIRE_ON should be set to HIGH. 5.12.1 6-wire Host Interface Protocol S5D4100X supports data communication based on 6-WIRE Host Interface Protocol. The address used is 15 bits, and the data depth is 8 bits. 6-WIRE is active in the section where the SCSN line is LOW. The upper 1-bit of the initial 16 bits indicates R/W (R: HIGH, W: LOW), and the remaining 15 bits indicate the address. The write (or read) data are after the address and before stop. In case of address or write data, the master (MCU) should send the data at the SCL rising edge, and the slave (S5D4100X) should receive the data at the SCL falling edge. On the contrary, for read data, the slave sends the data at the SCL falling edge, and the master receives the data at the SCL rising edge. Timing Chart (Data sequence in write/read of n registers) Remark MS: MASTER Send to SLAVE MR: MASTER Receive SS: SLAVE Send to MASTER SR: SLAVE Receive
Start SCSN
Stop
SCL
SDA3
W
ADDR[11]
ADDR[7]
ADDR[3]
DATA1[7]
DATA1[3]
DATA2[7]
DATAn[3]
SDA2
ADDR[14]
ADDR[10]
ADDR[6]
ADDR[2]
DATA1[6]
DATA1[2]
DATA2[6]
DATAn[2]
SDA1
ADDR[13]
ADDR[9]
ADDR[5]
ADDR[1]
DATA1[5]
DATA1[1]
DATA2[5]
DATAn[1]
SDA0
ADDR[12] MS SR MS
ADDR[8] SR MS
ADDR[4] SR MS
ADDR[0] SR
DATA1[4] MS SR MS
DATA1[0] SR
DATA2[4] MS SR
DATAn[0] SR
Figure 31. 6-wire Host Interface Write Data Sequence (Sending n data)
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Start SCSN
Stop
SCL
SDA3
R
ADDR[11]
ADDR[7]
ADDR[3]
DATA1[7]
DATA1[3]
DATA2[7]
DATAn[3]
SDA2
ADDR[14]
ADDR[10]
ADDR[6]
ADDR[2]
DATA1[6]
DATA1[2]
DATA2[6]
DATAn[2]
SDA1
ADDR[13]
ADDR[9]
ADDR[5]
ADDR[1]
DATA1[5]
DATA1[1]
DATA2[5]
DATAn[1]
SDA0
ADDR[12] MS SR MS
ADDR[8] SR MS
ADDR[4] SR MS
ADDR[0] SR SS
DATA1[4] MR SS
DATA1[0] MR SS
DATA2[4] MR
DATAn[0] MR
Figure 32. 6-wire Host Interface Read Data Sequence (Reading n data)
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5.12.2 I2C Host Interface Protocol S5D4100X supports data communication based on I2C Protocol. The slave address which corresponds to the device ID is 7 bits (binary "0000101"). The address used is 15 bits, and the data depth is 8 bits. Therefore, in order to access an address, the product indexes 2 bytes (Address MSB, Address LSB), and uses the 1-byte data depth. Since the address bits are 15 bits, the 1 byte for address MSB is "X A14 A13 A12 A11A10 A9 A8", and the 1 byte for address LSB is Binary "A7 A6 A5 A4 A3 A2 A1 A0". 1) Timing Chart (Data sequence in write/read of n registers)
SDA SCL Start
Device ID
W
Address MSB
ACK Address LSB Data 1
ACK
SDA SCL
ACK SDA SCL ACK Data 2 Data n
ACK
Stop
Figure 33. I2C Host Interface Write Data Sequence
SDA SCL Start
Device ID
R
Address MSB
ACK Address LSB Data 1
ACK
SDA SCL
ACK SDA SCL ACK Stop Data 2 Data n
ACK
Figure 34. I2C Host Interface Read Data Sequence In the above timing chart, the device ID (slave address) and read/write byte are as follows.
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0
0
0
0
1
0
1
R/W
DEVICE ID
Address is 15 bits, and for the remaining upper 1 bit of the address MSB can be 0 or 1 (Don't Care: X).
2) Example Write to one register Send Start Signal Send Device ID Byte (R/W Bit = LOW) Send Address MSB Send Address LSB Send Data to Address Send Stop Signal Write to four consecutive registers Send Start Signal Send Device ID Byte (R/W Bit = LOW) Send Address MSB Send Address LSB Send Data 1 to Address Send Data 2 to (Address + 1) Send Data 3 to (Address + 2) Send Data 4 to (Address + 3) Send Stop Signal Read from one register Send Start Signal Send Device ID Byte (R/W Bit = HIGH) Send Address MSB Send Address LSB Receive Data from Address Send Stop Signal Read form four consecutive control registers Send Start Signal Send Device ID Byte (R/W Bit = HIGH) Send Address MSB Send Address LSB Receive Data 1 from Address Receive Data 2 from (Address + 1) Receive Data 3 from (Address + 2) Receive Data 4 from (Address + 3) Send Stop Signal
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5.12.3 3-wire Host Interface Protocol S5D4100X supports data communication based on 3-WIRE Host Interface Protocol. The address used is 15 bits, and the data depth is 8 bits. 3-WIRE is active in the section where the SCSN line is LOW. The upper 1 bit of the initial 16 bits indicates R/W (R: HIGH, W: LOW), and the remaining 15 bits indicate the address. The write (or read) data are after the address and before stop. In case of address or write data, the master (MCU) should send the data at the SCL rising edge, and the slave (S5D4100X) should receive the data at the SCL falling edge. On the contrary, for read data, the slave sends the data at the SCL falling edge, and the master receives the data at the SCL rising edge. Remark MS: MASTER Send to SLAVE MR: MASTER Receive SS: SLAVE Send to MASTER SR: SLAVE Receive
MS SR Start SCSN
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR Stop
SCL
SDA
W
ADDRESS
DATA
15 bits Address
8 bits Data
Figure 35. 3-wire Host Interface Write Data Sequence
MS SR Start SCSN
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
MS SR
SS MR
SS MR
SS MR
SS MR
SS MR
SS MR
SS MR
SS MR
SS MR Stop
SCL
SDA
R
ADDRESS
DATA
15 bits Address
8 bits Data
Figure 36. 3-wire Host Interface Read Data Sequence
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DATASHEET
S5D4100X
5.12.4 Pulse Width Modulation (PWM) PWM lets the high and low signal to have a regular width. S5D4100X has 2 PWMs; PWM0 and PWM1. To use the PWMs, Register PWM0_SEL and PWM1_SEL should be set to HIGH. In order to set PWM, PWM_PRE_SCALE should be set first. Register PWM_PRE_SCALE is 0 ~ 3, which makes PRE_SCALER to generate the clocks of bypass, 2-division, 4-division and 8-division, respectively, of CKOSC. PWM0/1 use the PRE_SCALER output as the clock, and send the HIGH signals in the unit of 256 clock for the value set in Register PWM_DATA0/1. If the final Register PWM_EN in the last output buffer is 1, the signal generated in PWM0/1 is displayed, and if it is 0, the function is disabled, and LOW signal is sent continuously. Then the signal is multiplexed by Register PWM0/1_SEL.
CKOSC
PRE_SCALE
PWM0 GPO0
1 0 PWM0_SEL
PWM0
PWM_PRE_SCALE
PWM_DATA0
PWM1 GPO1 PWM_DATA1 PWM_EN
1 0
PWM1
PWM1_SEL
Figure 37. PWM 5.12.5 General Purpose Outputs (GPO's) General Purpose Output (GPO) sends HIGH or LOW signal to Pins GO0~GO5 for the value set in GPO0 ~ GPO5 when Register SERIAL_ON is HIGH, and MCU controls the register. The product has 6 GPOs; GPO0 ~ GPO5. GPO0 and GPO1 can be sent to Pins PWM0/PWM1, regardless of Register SERIAL_ON, if Register PWM0_SEL and PWM1_SEL are LOW.
46
DATASHEET
S5D4100X
5.13 DATA OUTPUT FORMATTER & SERIAL INTERFACE 5.13.1 Output Formatter S5D4100X supports output of various formats to meet various interfaces. -- R/G/B Parallel Output for RGB-Pixel Panel -- R/G/B Serial Output for RGB-Dot-Pixel LCD Panel -- ITU-R656, 8-Bit 4:2:2 Data with Embedded Sync Output for External Application 5.13.2 R/G/B Parallel output S5D4100X sends 24-bit data to LCD panel via Output Pins RO0~RO7, GO0~GO7 and BO0~BO7, by setting Register SERIAL_ON to LOW for RGB-Pixel LCD Panel (Figure 38).
ODD Line
RGB
RGB
RGB
RGB
RGB
RGB
EVEN Line
RGB
RGB
RGB
RGB
RGB
RGB
ODD Line
RGB
RGB
RGB
RGB
RGB
RGB
EVEN Line
RGB
RGB
RGB
RGB
RGB
RGB
Figure 38. Parallel interface Panel Architecture The product should support parallel data interface with the panel by sending 24-bit R/G/B data (Figure 39) in 1 clock in the R/G/B parallel output Interface mode.
CLOCK Horizontal Active R Data[7:0] G Data[7:0] B Data[7:0] R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R7 G7 B7 ... ... ... Parallel Output Interface Data (24-bit)
Figure 39. Parallel Output Data
47
DATASHEET
S5D4100X
5.13.3 RGB Serial output S5D4100X sends the data in R/G/B serial output format through R Channel (OUTPUT PIN RO0~RO7) to correspond to RGB-Dot-Pixel LCD Panel (Figure 40). The product can send data to meet various delta type panel spec by setting Register SERIAL_ON HIGH, and Register ODD_SPL and EVEN_SPL. The R, G, B dot layout in Figure 40 may be changed depending on the panel spec.
ODD Line
R
G
B
R
G
B
..........
EVEN Line
G
B
R
G
B
R
..........
ODD Line
R
G
B
R
G
B
..........
EVEN Line
G
B
R
G
B
R
..........
Figure 40. Delta Type Panel Architecture Unlike the existing parallel interface panel (Figure 40) in which R/G/B data are sent in 1 clock (24-bit Parallel Output Interface Data), in the serial output interface panel, only one data (8-bit serial interface data) out of R/G/B data can be sent in 1 clock. (See Figure 41)
CLOCK Horizontal Active R Data[7:0] G Data[7:0] B Data[7:0] Serial Output Data[7:0] R1 G1 B1 R1 R2 G2 B2 G2 R3 G3 B3 B3 R4 G4 B4 R4 R5 G5 B5 G5 R6 G6 B6 B6 R7 G7 B7 R7 ... ... ... u Serial Output Interface Data (8-bit) Internal Signal Processing Data (24-bit)
Figure 41. Serial Output Data
48
DATASHEET
S5D4100X
This table shows the sequence of R, G, B dot for register setting. Register HMODE = 1 (Based on DE Rising) Register ODD_SPL/ Register EVEN_SPL 000 001 010 011 100 101 110 111 R G B R G B R B B R G G R G B or G B R or B R G depending on the relationship between HS and DE Not use R (B (G or G (R (B or B (G (R depending on the relationship between HS and DE Not use R, G, B output order Register HMODE = 0 (Based on HS Falling) R, G, B output order
Not use G (R (B B (G (R Not use
In the delta type panel in Figure 40, EVEN Line is the vertically same timing data with ODD Line, but is deviated by 0.5 Dot due to the panel structure. In order to improve the delta structure display quality, set Register 0X000E[0] to 1, and set the compensation type of 0x000E[1]. If (Compensation Type = 0) then, Compensated Pixel = (Previous Pixel + Current Pixel)/2, if (Compensation Type = 1) then, Compensated Pixel = (Current Pixel + Next Pixel)/2
5.13.4 ITU-656 output S5D4100X sends data in serial output format to the panel via the R channel, and at the same time the ITU-R656 data to Channel B (OUTPUT PIN BO0 ~ BO7) to use another application. Various path signals may be transformed to ITU-656 format in accordance with Register EN_656OUTSEL when Register SERIAL_ON and Register ENC_ON are HIGH.
49
DATASHEET
S5D4100X
5.14 POWER DOWN CONTROL Power Down function is implemented as turning off each block and output pad. In case of Power Down Enable, you must set register value as below. -- Block Enable Register GBI_ON(0x0001[5]) = 0 GBO_ON(0x0001[4]) = 0 BU_ON(0x0001[3]) = 0 OSD_ON(0x0001[2]) = 0 ENC_ON(0x0001[1]) = 0 SC_ON(0x0001[0]) = 0 -- PLL Enable Register PLL_PW_DN(0x000B[4]) = 1 -- Pad Output Enable Register PD_CTRL(0x0019[3]) = 1 RO_CTRL(0x0019[2]) = 1 GO_CTRL(0x0019[1]) = 1 BO_CTRL(0x0019[0]) = 1 In case of Power Down disable, you must set the value for before.
50
DATASHEET
S5D4100X
6. REGISTER MAP
Legend Address Bits No. Register Name Address Name (Default Value) Function Description R/W
6.1 GLOBAL 0x0000 7:6 GLOBAL_BLOCK_CONTROL1 (Default: 0x 08) Reserved ITU-656 Input Channel Select 5 ITU656_CH 0: Uses the pins YI7~YI0 for 656 data input, VCKI pin for clock input, and VD pin for VS input. 1: Uses the pins CI7~CI0 for 656 data input, HD pin for clock input, and FLD pin for VS input. Dither Block ON/OFF Select 4 DTH_ON 0: Dither OFF 1: Dither ON Serial Output Mode ON/OFF 3 SERIAL_ON 0: Sends 24-bit R/G/B data to the pins RO7~RO0 / GO7~GO0 / BO7~BO0 1: Sends 8-bit serial data to RO7~RO0 The ON/OFF register determines whether to use the internally created test pattern as the scaler input regardless of the input image. 0: Test Pattern OFF 1: Test Pattern ON Back Ground Color ON/OFF Register BG_COLOR_ ON If Back Ground Color is ON, a single color image is entered to the gamma block to display the single color image on the screen regardless of the input image. The color is selected by the values 0x008A~0x008C. 0: Back Ground Color OFF 1: Back Ground Color ON Pseudo Sync RUN Mode 0 FREE_RUN The ON/OFF register determines whether to display Pseudo Sync if no Sync is received to S5D4100X (in case of 656, when no data is received). 0: Pseudo Sync Output OFF 1: Pseudo Sync Output ON R/W
2
TEST_PAT_ON
1
51
DATASHEET
S5D4100X
0x0001
GLOBAL_BLOCK_CONTROL2 (Default: 0x 3F) If HIF Pin is 1, the default value is 3-wire. In order to use Six-Wire, SIX_WIRE_ON should be set to 1. 0: 3-WIRE MODE 1: 6-WIRE MODE Reserved Input Domain Clock ON/OFF
R/W
7
SIX_WIRE_ON
6 5 GBI_ON
0: Input Domain Clock OFF 1: Input Domain Clock ON Output Domain Clock ON/OFF 0: Output Domain Clock OFF 1: Output Domain Clock ON BOOSTUP Clock ON/OFF 0: BOOSTUP Clock OFF 1: BOOSTUP Clock ON OSD Clock ON/OFF 0: OSD Clock OFF 1: OSD Clock ON ENCODER Clock ON/OFF 0: ENCODER Clock OFF 1: ENCODER Clock ON SCALER Clock ON/OFF 0: SCALER Clock OFF 1: SCALER Clock ON
4
GBO_ON
3
BU_ON
2
OSD_ON
1
ENC_ON
0
SC_ON
0x0002
GLOBAL_TEST_PATTERN_CONTROL (Default: 0x 3F) YUV TEST Domain Select
R/W
7
TP_YCbCr_ON
If TP_YUV_ON is 1, TEST_PATTERN is created in the YCbCr domain, and if TP_YUV_ON is 0, TEST_PATTERN is created in the RGB domain. 0: RGB Domain Select Tests Sync ON 1: YCbCr Domain Select
6
TP_SYNC_ON
If TEST_PAT_ON and TP_SYNC_ON, the internally created test sync is used as the input for the scaler. Timing for test sync is described in Figure 11. 0: Test Sync OFF 1: Test Sync ON Test pattern RGB ON/OFF Register 2 bits are assigned and controlled for RGB respectively. [5:4] - R , [3:2] - G , [1:0] - B See Table 5.1 for description on the 2 bits. If TP_YCbCr_ON is 1, YCbCr is controlled instead of RGB.
5:0
TP_RGB_ON
52
DATASHEET
S5D4100X
0x0003 7:0 TP_SEL
GLOBAL_TEST_PATTERN_SELECT (Default: 0x 00) Test Pattern Select
R/W
The register is used for selection of test pattern. Figure 12 describes the register, and Figure 13 shows the types of patterns available.
0x0004
GLOBAL_TEST_PATTERN_CONST_LEVEL_CONTROL (Default: 0x 00) Constant Test Pattern Level Control
R/W
7:0
TP_CONST_ LEVEL
The register is enabled when Pattern No. 6 is selected in TP_SEL. The register is used to select a specific level. Details are described in 5.5.2 Test Pat. Gen.
0x0005
GLOBAL_TEST_PATTERN_CONST_WIDTH_CONTROL (Default: 0x 00) Constant Test Pattern Width Control
R/W
7:0
TP_CONST_ WIDTH
The register is enabled when Pattern No. 6 is selected in TP_SEL. The register is used to select a width of each level. Details are described in 5.5.2 Test Pat. Gen.
0x0006
GLOBAL_INPUT_CLOCK_AND_MASK_CONTROL (Default: 0x 03) Input Clock Delay
R/W
7:4
CKI_DLY
The register delays the clock selected by ITU656_CH. The most significant bit of the 4 bits is the inversion signal. Changeable 2-Times Scaler Output Clock Phase 0: Normal 1: Phase Reverse Input Clock Select (See Figure 7 Clock System) 0: CKOSC Select 1: VCK Select Input Blank Data Mask ON/OFF The register masks the blank area to black. 0: Mask OFF 1: Mask ON Input Rolling Data Mask ON/OFF The register masks the unnecessary image displayed due to rolling at moving of screen position. 0: Mask OFF 1: Mask ON
3
CKI2_PHASE
2
CKI_SEL
1
BLANK_MASK_ ON
0
ROLLING_ MASK_ON
53
DATASHEET
S5D4100X
0x0007
GLOBAL_OUTPUT_CLOCK_AND_SYNC_CONTROL (Default: 0x 00) Output Clock Delay
R/W
7:4 3 2
CKO_DLY
The register controls delay for the output clock sent to the PCKO pin. The most significant bit of the 4 bits is the inversion signal. Reserved Output Date Enable Signal (PDEO) Polarity
OPOL_DE
0: HIGH Active 1: LOW Active Output VS (PVSO) Polarity 0: LOW Active 1: HIGH Active Output HS (PHSO) Polarity 0: LOW Active 1: HIGH Active
1
OPOL_VS
0
OPOL_HS
0x0008 7:4 M2CK_PHASE
GLOBAL_CLOCK_AND_SYNC_CONTROL (Default: 0x 04) Encoder Clock Phase Control
R/W
The register controls the clock phase when V601 is 1. It is controlled in the 2MUL block in Figure 7. CKOSC Clock Select 0: XI Pin 1: The clock selected by ITU656_CH (VCK or VD Pin) PDEO Delay Output Data Enable Signal (PDEO Pin)
3
CKOSC_SEL
2:0
PDEO_DLY
0x0009 7 6 5 4 3 2 1 0 CKO_SEL GPO5 GPO4 GPO3 GPO2 GPO1 GPO0 Reserved
GLOBAL_GPO (Default: 0x 40) CKO Domain Clock Select (See Figure 7 Clock System) 0: CKOSC Clock 1: PLL output Clock General Purpose Output #5 (See 5.12.4) General Purpose Output #4 (See 5.12.4) General Purpose Output #3 (See 5.12.4) General Purpose Output #2 (See 5.12.4) General Purpose Output #1 (See 5.12.4) General Purpose Output #0 (See 5.12.4)
R/W
54
DATASHEET
S5D4100X
0x000A
GLOBAL_VFP_CLOCK_DOWN (Default: 0x 01)
R/W
7
VFP_CKO_DN
The ON/OFF signal used to determine whether to fix the PCKO clock in VFP section to LOW. 0: Normal mode 1: Clock Down The register designates the number of lines in which PCKO clock in VFP section should not be fixed to LOW when VFP_CKO_DN is HIGH.
6:0
VDOWN
0x000B
GLOBAL_PWM_CONTROL (Default: 0x 20)
R/W
7:6
PWM_PRE_ SCALE
Determines the level of PWM duty to divide based on CKOSC clock when using the pulse width modulation 00: CKOSC 01: 2_Divided CKOSC 10: 4_Divided CKOSC 11: 8_Divided CKOSC Pulse Width Modulation Enable 0: Disable (LOW Output Signal) 1: Enable (PWM Output Signal) PLL Power Down 0: Disable 1: Enable Reserved PWM1 is sent if PWM1_SEL is HIGH, or GPO1 signal if it is LOW. PWM0 is sent if PWM0_SEL is HIGH, or GPO0 signal if it is LOW.
5
PWM_EN
4 3:2 1 0
PLL_PW_DN
PWM1_SEL PWM0_SEL
0x000C
GLOBAL_PWM_DATA0 (Default: 0x 00)
R/W
7
PWM_DATA0
Pulse Width Modulation 0 Creates, with the 256 clocks durations created by PWM_PRE_SCALE, the pulse of HIGH for the clock durations set in PWM_DATA0 and of LOW for the remaining clock durations.
0x000D
GLOBAL_PWM_DATA1 (Default: 0x 00)
R/W
7
PWM_DATA1
Pulse Width Modulation1 Creates, with the 256 clocks durations created by PWM_PRE_SCALE, the pulse of HIGH for the clock durations set in PWM_DATA1 and of LOW for the remaining clock durations.
55
DATASHEET
S5D4100X
0x000E 7:6
GLOBAL_SERIAL_CONTROL1 (Default: 0x 27) Reserved Selects the reference of serial data between HACT and HS.
R/W
5
HMODE_SEL
Since R/G/B of the serial format data should be transmitted in series, the internal counter is used. The register determines if the counter is started for HACT or HS. This indicates the section at which the valid data is transmitted via the actual serial output formatter. 0: HS 1: HACT
4
LINE_INV
The signal exchanges ODD line and EVEN line. LINE_INV is used for vertical inversion display to set the color. This register is used to give delay on the data in serial interface when HS is fixed. This is added to meet various panel structures. The default is DATA_DLY = [ 01]. Depending on the panel structure, the EVEN line may starts earlier/later than ODD line by 0.5 pixel. Therefore, compensation type can be divided as follows. 0: Compensation between the previous pixel and the current pixel 1: Compensation between the current pixel and the next pixel Although the EVEN Line is of the same timing data with the ODD Line, but it may be deviated by 0.5 Dot due to the panel structure. In order to improve the display quality of the delta structure, set Register 0X000E[0] to 1, and set the compensation type of 0x000E[1].
3:2
DATA_DLY
1
COMP_TYPE
0
EVEN_COMP_ SEL
56
DATASHEET
S5D4100X
0x000F 7
GLOBAL_SERIAL_CONTROL2 (Default: 0x01) Reserved Sends the data in the ODD line in the following sequence. If 0X000F[6] = 0, ... R G B R G B ... If 0X000F[6] = 1, ... R B G R B G ...
R/W
6:4
ODD_SPL
The first data of the line is determined in accordance with 0X000F[5:4]. If HMODE_SEL = HIGH, the first data are ODD_SPL[1:0]= [00] R, ODD_SPL[1:0]= [01] G, ODD_SPL[1:0]= [10] B. If HMODE_SEL =LOW, because the counter is fixed, the first data may vary. 0x000F[5:4] = [11] is not used. Reserved Sends the data in the EVEN line in the following sequence. If 0X000F[2] = 0, ... R G B R G B ... If 0X000F[2] = 1, ... R B G R B G ...
3
2:0
EVEN_SPL
The first data of the line is determined in accordance with 0X000F[1:0]. If HMODE_SEL = HIGH, the first data are EVEN_SPL[1:0]= [00] R, EVEN_SPL[1:0]= [01] G, EVEN_SPL[1:0]= [10] B. If HMODE_SEL = LOW, because the counter is fixed, the first data may vary. 0x000F[1:0] = [11] is not used.
0x0010 7:4 3 2:0 DEMODE HOUTMIN[10:8]
GLOBAL_OUTPUT_MASK_HMIN_MSB (Default: 0x 08) Reserved Horizontal Output MASK Mode Select 0: SYNC MODE 1: DE MODE Horizontal Output MASK min number
R/W
0x0011 2:0 HOUTMIN[7:0]
GLOBAL_OUTPUT_MASK_HMIN_LSB (Default: 0x 00) Horizontal Output MASK min number
R/W
0x0012 7:3 2:0 HOUTMAX [10:8]
GLOBAL_OUTPUT_MASK_HMAX_MSB (Default: 0x 00) Reserved Horizontal Output MASK max number
R/W
0x0013 2:0 HOUTMAX[7:0]
GLOBAL_OUTPUT_MASK_HMAX_LSB (Default: 0x 00) Horizontal Output MASK max number
R/W
57
DATASHEET
S5D4100X
0x0014 7:3 2:0 VOUTMIN[10:8]
GLOBAL_OUTPUT_MASK_VMIN_MSB (Default: 0x 00) Reserved Vertical Output MASK min number
R/W
0x0015 2:0 VOUTMIN[7:0]
GLOBAL_OUTPUT_MASK_VMIN_LSB (Default: 0x 00) Vertical Output MASK min number
R/W
0x0016 7:3 2:0 VOUTMAX[10:8]
GLOBAL_OUTPUT_MASK_VMAX_MSB (Default: 0x 00) Reserved Vertical Output MASK max number
R/W
0x0017 2:0 VOUTMAX[7:0]
GLOBAL_OUTPUT_MASK_VMAX_LSB (Default: 0x 00) Vertical Output MASK max number
R/W
0x0018
GLOBAL_VFP_HS_DOWN (Default: 0x 00)
R/W
7
HS_DN_ON
The ON/OFF signal used to determine whether to fix the PHSO in VFP section to LOW. 0: Normal mode 1: HS down The register designates the number of lines in which PHSO in VFP section should not be fixed to LOW when HS_DN_ON is HIGH.
6:0
HS_DN
0x0019 3 PD_CTRL
GLOBAL_PAD_CONTROL (Default: 0x00) PVSO/PHSO/PDEO/PCKO Output Enable Signal 0: Output enable 1: Output Disable RO0 ~ RO7 Output Enable Signal 0: Output enable 1: Output Disable GO0 ~ GO7 Output Enable Signal 0: Output enable 1: Output Disable BO0 ~ BO7 Output Enable Signal 0: Output enable 1: Output Disable
R/W
2
RO_CTRL
1
GO_CTRL
0
BO_CTRL
58
DATASHEET
S5D4100X
6.2 TIMING GENERATOR 0x0020 TG_TIMING_CONTROL (Default: 0x84) Auto TOTAL setting register 7 AUTO_TOTAL Determines whether to use the internally calculated value or the register setting for the addresses 0x0021 ~ 0x0025. 1: Auto Set (Internally calculated value) 0: Manual Set (Register setting) 6 5 4:3 2 DET_FRAME HVSO_DET For inversion, resets and detects TG sync creation to create output sync. Reserved Sets the TG detection start frame (1 ~ 4 Frame). Sets the number of frames to be referred for detection in order to create normal sync after inversion of HVSO_DET. Reserved PLL PFD Input Signal Select (See Figure 16) 1:0 PLL_FIN_SEL 0: Pre-Divider Output 1: Not Used 2, 3: HS R/W
0x0021 7:0 ADDED_LINE
TG _ADDED_LINE(Default: 0x 01) Sets the difference value between the odd and the even field.
R/W
0x0022 7:3 2:0 HTOTAL[10:8] Reserved
TG _INPUT_HTOTAL_MSB (Default: 0x 03) Horizontal Input Total Pixel Value
R/W
0x0023 7:0 HTOTAL[7:0]
TG _INPUT_HTOTAL_LSB (Default: 0x 5A) Horizontal Input Total Pixel Value
R/W
0x0024 7:3 2:0 VTOTAL[10:8] Reserved
TG _INPUT_VTOTAL_MSB (Default: 0x 01) Vertical Input Total Pixel Value
R/W
0x0025 7:0 VTOTAL[7:0]
TG _INPUT_VTOTAL_LSB (Default: 0x 07) Vertical Input Total Pixel Value
R/W
59
DATASHEET
S5D4100X
0x0026 7:3 2:0 H_STR[10:8]
TG _INPUT_H_START_MSB (Default: 0x 00) Reserved Horizontal Active Input Start Point
R/W
0x0027 7:0 H_STR[7:0]
TG _INPUT_H_START_LSB (Default: 0x86) Horizontal Active Input Start Point
R/W
0x0028 7:3 2:0 V_STR[10:8]
TG _INPUT_V_START_MSB (Default: 0x 00) Reserved Vertical Active Input Start Point
R/W
0x0029 7:0 V_STR[7:0]
TG _INPUT_V_START_LSB (Default: 0x 14) Vertical Active Input Start Point
R/W
0x002A 7:0 HOFP
TG _HOFP (Default: 0x 2B) Horizontal Output Front Porch
R/W
0x002B 7:0 HOSW
TG _HOSW (Default: 0x 2E) Horizontal Output Sync Width
R/W
0x002C 7:3 2:0 HOBP [10:8] Reserved
TG L_HOBP_MSB (Default: 0x 00) Horizontal Output Back Porch
R/W
0x002D 7:0 HOBP[7:0]
TG_HOBP_LSB (Default: 0x 32) Horizontal Output Back Porch
R/W
0x002E 7:0 VOFP[7:0]
TG_VOFP (Default: 0x 01) Vertical Output Front Porch
R/W
0x002F 7:0 VOSW[7:0]
TG_VOSW (Default: 0x 03) Vertical Output Front Porch
R/W
60
DATASHEET
S5D4100X
0x0030 7:3 2:0 HIAS [10:8] Reserved
TG_HIAS_MSB (Default: 0x 02) Horizontal Input Active Size
R/W
0x0031 7:0 HIAS[7:0]
TG_HIAS_LSB (Default: 0x D0) Horizontal Input Active Size
R/W
0x0032 7:3 2:0 VIAS [10:8] Reserved
TG_VIAS_MSB (Default: 0x 00) Vertical Input Active Size
R/W
0x0033 7:0 VIAS[7:0]
TG_VIAS_LSB (Default: 0x F0) Vertical Input Active Size
R/W
0x0034 7:3 2:0 HOAS [10:8] Reserved
TG_HOAS_MSB (Default: 0x 00) Horizontal Output Active Size
R/W
0x0035 7:0 HOAS[7:0]
TG_HOAS_LSB (Default: 0x E0) Horizontal Output Active Size
R/W
0x0036 7:3 2:0 VOAS [10:8] Reserved
TG_VOAS_MSB (Default: 0x 00) Vertical Output Active Size
R/W
0x0037 7:0 VOAS[7:0]
TG_VOAS_LSB (Default: 0x F0) Vertical Output Active Size
R/W
0x0038 7:0 PLL_P[7:0]
TG_PLL_P_MSB (Default: 0x 04) PLL Programmable Pre-Divider
R/W
0x0039 7:0 PLL_P[7:0]
TG_PLL_P_LSB (Default: 0x 38) PLL Programmable Pre-Divider
R/W
61
DATASHEET
S5D4100X
0x003A 7:6 5:0 PLL_M [13:8] Reserved
TG_PLL_M_MSB (Default: 0x 0C) PLL Programmable Main-Divider
R/W
0x003B 7:0 PLL_M[7:0]
TG_PLL_M_LSB (Default: 0x 21) PLL Programmable Main-Divider
R/W
0x003C 7:5 4:0 PLL_S Reserved
TG_PLL_S (Default: 0x 03) PLL Programmable Post Scaler, S= PLL_S[ 4: 2 ] + PLL_S[ 1: 0 ]
R/W
0x003D 7:0 PLL_M_FRACT
TG_PLL_M_FRACT_LSB (Default: 0x 92) TG's PLL_M register Fraction bits
R/W
0x0042 7:6 5:0 HOFFSET[13:8] Reserved
TG_HOFFSET_MSB (Default: 0x 00) Horizontal Output Active Point Offset Delay
R/W
0x0043 7:0 HOFFSET[7:0]
TG_HOFFSET_LSB (Default: 0x 84) Horizontal Output Active Point Offset Delay
R/W
0x0044 7:6 5:0 HOFFSET_ODD [13:8] Reserved
TG_HOFFSET_ODD_MSB (Default: 0x 00)
R/W
Horizontal Output Active Point Offset Delay. (Odd Field Only)
0x0045 7:0 HOFFSET_ODD [7:0]
TG_HOFFSET_ODD_LSB (Default: 0x 00) Horizontal Output Active Point Offset Delay. (Odd Field Only)
R/W
0x0046 7:4 3:0 HPOS[11:8] Reserved
TG_HPOS_MSB (Default: 0x 00) Horizontal Position (Engineering Test Mode, User Forbidden)
R/W
62
DATASHEET
S5D4100X
0x0047 7:0 HPOS[7:0]
TG_HPOS_LSB (Default: 0x 00) Horizontal Position (Engineering Test Mode, User Forbidden)
R/W
0x0048 7:0 VPOS[7:0]
TG_VPOS (Default: 0x 00) Vertical Position (Engineering Test Mode, User Forbidden)
R/W
0x004B 7:0 VMIN_ODD[7:0]
TG_VMIN_ODD Odd Field Output Vertical min number
RO
0x004C 7:0 VMIN_EVEN[7:0]
TG_VMIN_EVEN Odd Field Output Vertical min number
RO
63
DATASHEET
S5D4100X
6.3 YC PROCESSOR 0x0050 7 6 SEL_DI Reserved Decoding domain select 0: YCbCr Domain 1: YUV Domain Input FIELD Signal Polarity 5 DI_FIELD_POL 0: Even Field HIGH, Odd Field LOW - 656 SPEC 1: Odd Field HIGH, Even Field LOW - Required Design HACT Signal Polarity 4 DI_HACT_POL 0: Active LOW - 656 SPEC 1: Active HIGH - Required Design VACT Signal Polarity 3 DI_VACT_POL 0: Active LOW - 656 SPEC 1: Active HIGH - Required Design Sync Generation Block Selection 2 DI_SYNC_GEN 0: New Adjustment (Required Design) 1: S5D0127X Version Chroma Sign Bit Determination 1 DI_C_SIGN 0: Positive Number - SPEC (Required Design) 1: 2's Complementary - Non SPEC Cb / Cr Signal Input Type Selection 0 DI_CBCR_SEL 0: CB Y CR Y CB Y ... - SPEC (Required Design) 1: CR Y CB Y CR Y ... - NON_SPEC YCP_SYNC_CONTROL (Default: 0x7C) R/W
64
DATASHEET
S5D4100X
0x0051 7 6 V601
YCP_SYNC_SELECT (Default: 0x80) 601/656 Data Input Select 0: ITU-R656 Format 1: ITU-R601 Format Reserved Input Masking Enable
R/W
5
MASK_ON
Input data is masked by the registers of 0X0057 ~ 0X005E. The register turns ON/OFF this masking process. 0: MASKING OFF 1: MASKING ON Internal 601 Field select 0: External Field 1: Internal Field Field Output Polarity 656 Data Input Hsync Select 0: 656 Data Hsync use 1: HD Pin Input Hsync use 656 Data Input Vsync Select
4 3 2
INT_FLD_SEL FIELD_OUT_POL DI_HS_SEL
1 0
DI_VS_SEL
0: 656 Data Vsync use 1: VD Pin Input Vsync use Reserved
0x0052 7:4 3:0 VS_ODD_DLY VS_EVEN_DLY
YCP_VSYNC_DELAY (Default: 0x10) Vsync Odd Field Vertical Delay Select Vsync Even Field Vertical Delay Select
R/W
0x0053 7:0 DI_HFP
YCP_DI_HFP (Default: 0x0A) Horizontal Front Porch for HSync Output
R/W
0x0054 7:0 DI_HSW
YCP_DI_HSW (Default: 0x1E) Horizontal Pulse Width for HSync Output
R/W
65
DATASHEET
S5D4100X
0x0055 7:0 DI_VFP
YCP_DI_VFP (Default: 0x02) Vertical Front Porch for VSync Output
R/W
0x0056 7:0 DI_VSW
YCP_DI_VSW (Default: 0x08) Vertical Pulse Width for VSync Output
R/W
This should be set to 0x01 if the setting should be made regardless of the scale factor.
0x0057 7:3 2:0 DI_HACT_MIN [10:8] Reserved
YCP_HACT_MIN_MSB (Default: 0x00) Horizontal Active Input Start Point
R/W
Sets the start point of the input image based on the rising time of the sync selected by DI_HS_SEL.
0x0058 7:0 DI_HACT_MIN [7:0]
YCP_HACT_MIN_LSB (Default: 0x00) Horizontal Active Input Start Point
R/W
Sets the start point of the input image based on the rising time of the sync selected by DI_HS_SEL.
0x0059 7:3 2:0 DI_HACT_MAX [10:8] Reserved
YCP_HACT_MAX_MSB (Default: 0x00) Horizontal Active Input End Point
R/W
Sets the end point of the input image based on the rising time of the sync selected by DI_HS_SEL.
0x005A 7:0 DI_HACT_MAX [7:0]
YCP_HACT_MAX_LSB (Default: 0x00) Horizontal Active Input End Point
R/W
Sets the end point of the input image based on the rising time of the sync selected by DI_HS_SEL.
0x005B 7:3 2:0 DI_VACT_MIN [10:8] Reserved
YCP_VACT_MIN_MSB (Default: 0x00) Vertical Active Input Start Point
R/W
Sets the start point of the input image based on the rising time of the sync selected by DI_VS_SEL.
66
DATASHEET
S5D4100X
0x005C 7:0 DI_VACT_MIN [7:0]
YCP_VACT_MIN_LSB (Default: 0x00) Vertical Active Input Start Point
R/W
Sets the start point of the input image based on the rising time of the sync selected by DI_VS_SEL.
0x005D 7:3 2:0 DI_VACT_MAX [10:8] Reserved
YCP_VACT_MAX_MSB (Default: 0x00) Vertical Active Input End Point
R/W
Sets the end point of the input image based on the rising time of the sync selected by DI_VS_SEL.
0x005E 7:0 DI_VACT_MAX [7:0]
YCP_VACT_MAX_LSB (Default: 0x00) Vertical Active Input End Point
R/W
Sets the end point of the input image based on the rising time of the sync selected by DI_VS_SEL.
0x005F 7:0 INT_FIELD_601_ TH
YCP_FIELD_601_TH (Default: 0x00) Internal 601 Field Threshold
R/W
Sets the threshold for creation of internal field when INT_FLD_SEL is HIGH.
0x0060 7:4 3:0 CORE_H CORE_L
YCP_CORE (Default: 0x00) EDGE Coring HIGH level (See Figure 10) EDGE Coring LOW level (See Figure 10)
R/W
0x0061 0: Filter0 1: Filter1 2: Not Use 3: Filter2
YCP_EDGE_CONTROL (Default: 0x54) EDGE Filter Select
R/W
7:6
EDGE_FIL_SEL
5:4 3:0
CORE_RATE EDGE_GAIN
EDGE Coring Gain (See Figure 10) EDGE Gain The default value 4 means x1. The higher the value, the edge strength increases, and vice versa. (See 0x006E.)
67
DATASHEET
S5D4100X
0x0062 7:0 YCP_BLACK
YCP_BLACK (Default: 0x00) Black Level of Y element
R/W
YOUT = (YIN - YCP_BLACK) * YCP_CONTRAST + YCP_BRIGHTNESS
0x0063 7:0 YCP_CONTRAST
YCP_CONTRAST (Default: 0x80) Contrast Control of Y element
R/W
YOUT = (YIN - YCP_BLACK) * YCP_CONTRAST + YCP_BRIGHTNESS
0x0064 7:0 YCP_ BRIGHTNESS
YCP_BRIGHTNESS (Default: 0x00) BRIGHTNESS Control of Y element 2's complement in negative number.
R/W
YOUT = (YIN - YCP_BLACK) * YCP_CONTRAST + YCP_BRIGHTNESS
0x0065 7:2 1:0 HUE[9:8] Reserved HUE Control
YCP_HUE_MSB (Default: 0x00)
R/W
2'complement between -512 and +511. The value is between -180 deg and +180 deg.
0x0066 HUE Control 7:0 HUE[7:0]
YCP_HUE_LSB (Default: 0x00)
R/W
2'complement between -512 and +511. The value is between -180 deg and +180 deg.
0x0067 7:0 SATURATION
YCP_SATURATION (Default: 0x80) SATURATION Control
R/W
68
DATASHEET
S5D4100X
0x0068 7:6 5 4 3 2 1 EN_HPOL EN_VPOL EN_FPOL EN_LIM16 EN_656OUTSEL Reserved
YCP_ENCODER_SELECT (Default: 0x18) 656 OUTPUT SELECT (See Table 2) Encoder Horizontal Active Polarity Select Encoder Vertical Active Polarity Select Encoder Field Polarity Select Encoder Data Range Select (1:16 ~ 240, 0:1~254) Encoder Vertical Timing Select 0: Vertical Active Signal Select 1: Vsync Signal Select
R/W
0
EN_VSO_SEL
0x0069 7:4 3:0 EN_CK_DLY
YCP_ENCODER_CLOCK_DELAY (Default: 0x00) Reserved Encoder Output Clock Delay
R/W
The register controls delay for the output clock sent to the Pin GO7 when the encoder runs. The most significant bit of the 4 bits is the inversion signal.
0x006A 7 6:3 2:0 IN_WIDTH[10:8] HOUT_DET
YCP_OUT_HSYNC_CONTROL_MSB (Default: 0x02) Horizontal Timing Detection Select 0:Falling Time 1:Rising Time Reserved Horizontal Timing Width (Used in timing detection)
R/W
0x006B 7:0 IN_WIDTH[7:0]
YCP_OUT_HSYNC_CONTROL_LSB (Default: 0xD0) Horizontal Timing Width (Used in timing detection)
R/W
0x006C 7 6:3 2:0 IN_LINE[10:8] VOUT_DET
YCP_OUT_VSYNC_CONTROL_MSB (Default: 0x00) Vertical Timing Detection Select 0: Falling Time 1: Rising Time Reserved Vertical Timing Line (Used in timing detection)
R/W
69
DATASHEET
S5D4100X
0x006D 7:0 IN_LINE[7:0]
YCP_OUT_VSYNC_CONTROL_LSB (Default: 0xF0) Vertical Timing Line (Used in timing detection)
R/W
0x006E 7 6:0 EDGE_LIM Reserved
YCP_EDGE_LIMIT (Default: 0x10) EDGE LIMIT (See Figure 10)
R/W
70
DATASHEET
S5D4100X
6.4 SCALER 0x0071 7:0 IVZOOM[23:16] SCALER_IVZOOM_MSB (Default: 0x20) Inversed Vertical Zoom Ratio (= VIAS/VOAS) R/W
0x0072 7:0 IVZOOM[15:8]
SCALER_IVZOOM_MID (Default: 0x00) Inversed Vertical Zoom Ratio (= VIAS/VOAS)
R/W
0x0073 7:0 IVZOOM[7:0]
SCALER_IVZOOM_LSB (Default: 0x00) Inversed Vertical Zoom Ratio (= VIAS/VOAS)
R/W
0x0075 7:0 IHZOOM[23:16]
SCALER_IHZOOM_MSB (Default: 0x2F) Inversed Horizontal Zoom Ratio (= VIAS/VOAS)
R/W
0x0076 7:0 IHZOOM[15:8]
SCALER_IHZOOM_MID (Default: 0x55) Inversed Horizontal Zoom Ratio (= VIAS/VOAS)
R/W
0x0077 7:0 IHZOOM[7:0]
SCALER_IHZOOM_LSB (Default: 0x55) Inversed Horizontal Zoom Ratio (= VIAS/VOAS)
R/W
0x0078 7:5 4:0 HSTR_OFFSET Reserved
SCALER_HSTR_OFFSET (Default: 0x00) Always 0 Setting
R/W
0x0079 7:5 4:0 VSTR_OFFSET Reserved
SCALER_VSTR_OFFSET (Default: 0x00) Always 0 Setting
R/W
71
DATASHEET
S5D4100X
0x007A 7:6 5:4 3 2:0 HFSEL VFSEL DP_ARCH
SCALER_FILTER_SELECT (Default: 0x04) Horizontal Scaling Filter Select Vertical Scaling Filter Select Scaler Frequency Control Select 0: Normal Data Control 1: abnormal Data Control Reserved
R/W
0x007B 7:5 4:0 VSTR_OFFSET_ ODD
SCALER_VSTR_OFFSET_ODD (Default: 0x00) Reserved Always 0 Setting
R/W
72
DATASHEET
S5D4100X
6.5 CONTRAST 0x0080 7:5 Reserved Decides the ratio of the contrast control area 00: 0 ~ 0.99609375 01: 0.5 ~ 1.49609375 10: 0 ~ 1.9921875 11: 0 ~ 3.984375 Reserved BLACK_CT Black level control type 1: Adjust R/G/B simultaneously based on R 0: Adjust R/G/B individually Contrast control type 0: Adjust R/G/B individually 1: Adjust R/G/B simultaneously based on R Brightness control type 0: Adjust R/G/B individually 1: Adjust R/G/B simultaneously based on R CONTRAST_CONTROL (Default: 0x17) R/W
5:4
CONT_TYPE
3 2
1
CONT_CT
0
BRIGHT_CT
0x0081 7:5 5:0 R_BLACK Reserved
CONTRAST_R_BLACK (Default: 0x00) Adjusts R Channel Black level
R/W
0x0082 7:5 5:0 G_BLACK Reserved
CONTRAST_G_BLACK (Default: 0x00) Adjusts G Channel Black level
R/W
0x0083 7:5 5:0 B_BLACK Reserved
CONTRAST_B_BLACK (Default: 0x00) Adjusts B Channel Black level
R/W
73
DATASHEET
S5D4100X
0x0084 7:0 R_CONTRAST
CONTRAST_R_CONTRAST (Default: 0x80) Adjusts R Channel Contrast level
R/W
0x0085 7:0 G_CONTRAST
CONTRAST_G_CONTRAST (Default: 0x80) Adjusts G Channel Contrast level
R/W
0x0086 7:0 B_CONTRAST
CONTRAST_B_CONTRAST (Default: 0x80) Adjusts B Channel Contrast level
R/W
0x0087 7:0 R_BRIGHT
CONTRAST_R_ BRIGHTNESS (Default: 0x00) Adjusts R Channel Brightness level
R/W
0x0088 7:0 G_BRIGHT
CONTRAST_G_ BRIGHTNESS (Default: 0x00) Adjusts G Channel Brightness level
R/W
0x0089 7:0 B_BRIGHT
CONTRAST_B_BRIGHTNESS (Default: 0x00) Adjusts B Channel Brightness level
R/W
0x008A 7:0 BG_COLOR_R
CONTRAST_BG_COLOR_R (Default: 0x00) R Channel Background Color If BG_COLOR_ON is HIGH, the color selected by BG_COLOR_R, BG_COLOR_G and BG_COLOR_B is displayed on the entire screen.
R/W
0x008B 7:0 BG_COLOR_G
CONTRAST_BG_COLOR_G (Default: 0x00) G Channel Background Color If BG_COLOR_ON is HIGH, the color selected by BG_COLOR_R, BG_COLOR_G and BG_COLOR_B is displayed on the entire screen.
R/W
0x008C 7:0 BG_COLOR_B
CONTRAST_BG_COLOR_B (Default: 0x00) B Channel Background Color If BG_COLOR_ON is HIGH, the color selected by BG_COLOR_R, BG_COLOR_G and BG_COLOR_B is displayed on the entire screen.
R/W
74
DATASHEET
S5D4100X
6.6 GAMMA 0x0090 0x00AF 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 RYAV1 RYAV2 RYAV3 RYAV4 RYAV5 RYAV6 RYAV7 RYAV8 RYAV9 RYAV10 RYAV11
RYAV4 RYAV32 RYAV31 RYAV30
RAM_R_LUT_1_2 RAM_R_LUT_31_32 RED Output (Y) Axis Value for Input (X) Axis Value 8, 16, ... , 240, 248, 255
Y
R/W R/W 8'h08 8'h10 8'h18 8'h20 8'h28 8'h30 8'h38 8'h40 8'h48 8'h50 8'h58 8'h60
RYAV12 RYAV13 RYAV14 RYAV15 RYAV16 RYAV17 RYAV18 RYAV19 RYAV20 RYAV21 RYAV22 RYAV23 RYAV24 RYAV25 RYAV26 RYAV27 RYAV28 RYAV29 RYAV30 RYAV31 RYAV32
RYAV3 RYAV2 RYAV1 X 0 8 16 24 32 .......... 240 248 255
8'h68 8'h70 8'h78 8'h80 8'h88 8'h90 8'h98 8'hA0 8'hA8 8'hB0 8'hB8 8'hC0 8'hC8 8'hD0 8'hD8 8'hE0 8'hE8 8'hF0 8'hF8 8'hFF
75
DATASHEET
S5D4100X
0x00B0 0x00CF 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 GYAV1 GYAV2 GYAV3 GYAV4 GYAV5 GYAV6 GYAV7 GYAV8 GYAV9 GYAV10 GYAV11
GYAV4 GYAV32 GYAV31 GYAV30
GAM_G_LUT_1_2 GAM_G_LUT_31_32 GREEN Output (Y) Axis Value for Input (X) Axis Value 8, 16, ... , 240, 248, 255
Y
R/W R/W 8'h08 8'h10 8'h18 8'h20 8'h28 8'h30 8'h38 8'h40 8'h48 8'h50 8'h58 8'h60
GYAV12 GYAV13 GYAV14 GYAV15 GYAV16 GYAV17 GYAV18 GYAV19 GYAV20 GYAV21 GYAV22 GYAV23 GYAV24 GYAV25 GYAV26 GYAV27 GYAV28 GYAV29 GYAV30 GYAV31 GYAV32
GYAV3 GYAV2 GYAV1 X 0 8 16 24 32 .......... 240 248 255
8'h68 8'h70 8'h78 8'h80 8'h88 8'h90 8'h98 8'hA0 8'hA8 8'hB0 8'hB8 8'hC0 8'hC8 8'hD0 8'hD8 8'hE0 8'hE8 8'hF0 8'hF8 8'hFF
76
DATASHEET
S5D4100X
0x00D0 0x00EF 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 BYAV1 BYAV2 BYAV3 BYAV4 BYAV5
BYAV31 BYAV32
GAM_B_LUT_1_2 GAM_B_LUT_31_32 BLUE Output (Y) Axis Value for Input (X) Axis Value 8, 16, ... , 240, 248, 255
Y
R/W R/W 8'h08 8'h10 8'h18 8'h20 8'h28 8'h30
BYAV6 BYAV7 BYAV8 BYAV9 BYAV10 BYAV11 BYAV12 BYAV13 BYAV14 BYAV15 BYAV16 BYAV17 BYAV18 BYAV19 BYAV20 BYAV21 BYAV22 BYAV23 BYAV24 BYAV25 BYAV26 BYAV27 BYAV28 BYAV29 BYAV30 BYAV31 BYAV32
0 8 16 24 32 .......... 240 248 255 BYAV4 BYAV3 BYAV2 BYAV1 X BYAV30
8'h38 8'h40 8'h48 8'h50 8'h58 8'h60 8'h68 8'h70 8'h78 8'h80 8'h88 8'h90 8'h98 8'hA0 8'hA8 8'hB0 8'hB8 8'hC0 8'hC8 8'hD0 8'hD8 8'hE0 8'hE8 8'hF0 8'hF8 8'hFF
77
DATASHEET
S5D4100X
6.7 OSD 0x0100 7 FADE_EN OSD_FADE_ENABLE, FONT_SIZE (Default: 0 x 00) Fade function enable. 0: Disable 1: Enable Fade function Speed Control 0: x 4 1: x 3 2: x 2 3: x 1 (for 1 frame) OSD ON/OFF Register 4 OSD_EN 0: Disable 1: Enable Determines the character horizontal size based on the default font size (12 * 18). For example, if CH_HSZ is 1, the character horizontal size is 24(12*2) pixel. 3:2 CH_HSZ 0: 12 1: 24 2: 36 3: 48 Determines the character vertical size based on the default font size (12 * 18). For example, if CH_VSZ is 3, the character vertical size is 36(18*2) pixel. 1:0 CH_VSZ 0: 18 1: 36 2: 54 3: 72 R/W
6:5
FADE_CTRL
0x0101 7 6:4 COL_SP Reserved
OSD_SPACE_SIZE (Default: 0 x 00) Controls the number of column spaces between the fonts. Column Space = COL_SP * CH_HSZ * 2 pixel
R/W
3:0
ROW_SP
Controls the number of row spaces between the fonts. The number of vertical pixels is determined in accordance with the character vertical size. For example, if ROW_SP is 2 and CH_VSZ is 2, the row spaces are 4 lines.
0x0102 7 6:0 OSD_HFONT Reserved
OSD_HFONT (Default: 0 x 00) The number of horizontal fonts of OSD
R/W
78
DATASHEET
S5D4100X
0x0103 7:6 5:0 OSD_VFONT Reserved
OSD_VFONT (Default: 0 x 00) The number of vertical fonts of OSD
R/W
0x0104 7:3 2:0 OSD_HSP[10:8] Reserved
OSD_HSP_MSB (Default: 0 x 00) Horizontal start point of OSD
R/W
0x0105 7:0 OSD_HSP[7:0]
OSD_HSP_LSB(Default: 0 x 00) Horizontal start point of OSD
R/W
0x0106 7:3 2:0 OSD_VSP[10:8] Reserved
OSD_VSP_MSB (Default: 0 x 00) Vertical start point of OSD
R/W
0x0107 7:0 OSD_VSP[7:0]
OSD_VSP_LSB (Default: 0 x 00) Vertical start point of OSD
R/W
0x0108 7 BDSH_TYPE_SEL
OSD_BORDER_SHADOW_COLTROL (Default: 0 x 00) Selects thickness of Border/Shadow 1: Border/Shadow is fixed to 1 pixel regardless of the character size. 0: Border/Shadow pixel interworks with the character size. See Figure 21.
R/W
6
BDSH_PASS
1: The font border/shadow is shifted to the next font if the right side of the current font is full. (When the next font is Borer/Shadow On) 0: Border/Shadow is displayed within the font area only. Controls Character Border/Shadow globally 1: Controls border/shadow with DSRAM[13] 0: Border/Shadow is disabled regardless of DSRAM[13] Selects Border or Shadow when Character Border/Shadow On (G_BDSH_EN = 1 & DSRAM[13]=1) 1: Border select 0: Shadow select Selects Character Border / Shadow Color as G_BDSH_EN = 1
5
G_BDSH_EN
4
BDSH_SEL
3:0
CH_BSC
79
DATASHEET
S5D4100X
0x0109 7 6:0 MCF_SEL N_MCF
OSD_MCF_CONTROL (Default: 0 x 00) Multi Color Font Mode Select 0: MCF3 mode (3 fonts combination) 1: MCF2 mode (2 fonts combination) Number of Multi-Colored RAM Font
R/W
0x010A 7:5 Reserved
OSD_BLINK_CONTROL (Default: 0 x 00) Blink duty (visible: invisible) Select 0: 0.5sec: 0.5sec 1: 1sec: 0.5sec 2: 0.5sec: 1sec 3: 1sec: 1sec 4: 1.5sec: 1.5sec 5: 2sec: 1sec 6: 1sec: 2sec 7: 2sec: 2sec Blink or No_Tone_Raster 1: Blink Enable Blink Color inversion 1: On 0: OFF 0: No tone Raster
R/W
4:2
BLNK_SEL
1 0
BL_NTRA BLNC_C
0x010B 7 6 G_RA_EN CH_TONE
OSD_HALF_TONE_CONTROL (Default: 0 x 00) 1: Global Raster Enable Character half Toning 1: Half tone is applied to the character 0: Half tone is not applied to the character OSD half Toning 1:Global Half Ton Enable 0:Half Tone Disable OSD half Tone Level Control 0: 0% OSD 1: 1/32 % OSD 0: disable (default)
R/W
5
G_HT_EN
4:0
HALF_TONE_ CTRL
2: 2/32% OSD 3: 3/32%OSD .... 31:31/33%OSD
80
DATASHEET
S5D4100X
0x010C 7:3 2 FRONT_OSD Reserved
OSD DSRAM CONTROL (Default: 0x7C) FRONT OSD ON (OSD mixing before scaling) 1: ON 0: OFF (Default) Designates the attribute or the display RAM attribute [15] 1: INT (Intensity) is selected for the display RAM attribute [15] 0: OSD HT_EN is selected for the display RAM attribute [15] Global attribute is applied if INT is not selected for DSRAM attribute 1: Intensity On 0: Intensity Off
R/W
1
DSRAM_ATTR_ CON G_INT
0
0x010D 7:5 4:0 FTRAM_CS_ START_ADDR[8]
OSD_FTRAM_CS_START_OFFSET_ADDR_MSB (Default: 0 x 00) Reserved Designates the Font RAM Checksum Start offset Address
R/W
0x010E 7:0
FTRAM_CS_START _ADDR[7:0]
OSD_FTRAM_CS_START_OFFSET_ADDR_LSB (Default: 0 x 00) Designates the Font RAM Checksum Start offset Address
R/W
0x010F 7:5 4:0 FTRAM_CS_END_ ADDR[8]
OSD_FTRAM_CS_END_OFFSET_ADDR_MSB (Default: 0 x 11) Reserved Designates the Font RAM Checksum End Offset Address
R/W
0x0110 7:0 FTRAM_CS_END_ ADDR[7:0]
OSD_FTRAM_CS_END_OFFSET_ADDR_LSB (Default: 0 x FF) Designates the Font RAM Checksum End Offset Address
R/W
0x0111 7:4 3:0 FTRAM_ CHECKSUM[11:8] Reserved
FTRAM_CHECKSUM_MSB
RO
Font RAM Checksum, Read Only
81
DATASHEET
S5D4100X
0x0112 7:0 FTRAM_ CHECKSUM[7:0]
FTRAM_CHECKSUM_LSB Font RAM Checksum, Read Only
RO
0x0113 7:1 0 DSRAM_CS_ START_ADDR[8]
DSRAM_CS_START_OFFSET_ADDR_MSB (Default: 0 x 00) Reserved Designates the Display RAM Checksum Start Offset Address
R/W
0x0114 7:0
DSRAM_CS_START _ADDR[7:0]
DSRAM_START_OFFSET_ADDR_LSB (Default: 0 x 00) Designates the Display RAM Checksum Start Offset Address
R/W
0x0115 7:1 0 DSRAM_CS_ END_ADDR[8]
DSRAM_CS_END_OFFSET_ADDR_MSB (Default: 0 x 01) Reserved Designates the Display RAM Checksum End Offset Address
R/W
0x0116 7:0 DSRAM_CS_ END_ADDR[7:0]
DSRAM_CS_END_OFFSET_ADDR_LSB (Default: 0 x C1) Designates the Display RAM Checksum End Offset Address
R/W
0x0117 7:0 DSRAM_ CHECKSUM[15:8]
DSRAM_CHECKSUM_MSB Displays RAM Checksum, Read Only
RO
0x0118 7:0 DSRAM_ CHECKSUM[7:0]
DSRAM_CHECKSUM_LSB Displays RAM Checksum, Read Only
RO
0x0119 7:2 1 0 DSRAM_CS_ END_FLAG FTRAM_CS_ END_FLAG Reserved
OSD_RAM_CHECKSUM_END_FLAG
RO
0 1 at the end of display RAM checksum 0 1 at the end of front RAM checksum
82
DATASHEET
S5D4100X
0x011A 7:4 3 2 1 0 DSRAM_ CHECKSUM_EN FTRAM_ CHECKSUM_EN DSRAM_CLRN
MEMORY CHECKSUM & CLEAR (Default: 0 x 00) Reserved DSRAM CHECKSUM START FTRAM CHECKSUM START DSRAM Clear Reserved
R/W
0x0120 7:0 LUT0[7:0]
OSD_LUT0 (Default: 0 x 00) Look Up Table #0
R/W
0x0121 7:0 LUT1[7:0]
OSD_LUT1 (Default: 0 x 00) Look Up Table #1
R/W
0x0122 7:0 LUT2[7:0]
OSD_LUT2 (Default: 0 x 00) Look Up Table #2
R/W
0x0123 7:0 LUT3[7:0]
OSD_LUT3 (Default: 0 x 00) Look Up Table #3
R/W
0x0124 7:0 LUT4[7:0]
OSD_LUT4 (Default: 0 x 00) Look Up Table #4
R/W
0x0125 7:0 LUT5[7:0]
OSD_LUT5 (Default: 0 x 00) Look Up Table #5
R/W
0x0126 7:0 LUT6[7:0]
OSD_LUT6 (Default: 0 x 00) Look Up Table #6
R/W
0x0127 7:0 LUT7[7:0]
OSD_LUT7 (Default: 0 x 00) Look Up Table #7
R/W
83
DATASHEET
S5D4100X
0x0128 7:0 LUT8[7:0]
OSD_LUT8 (Default: 0 x 00) Look Up Table #8
R/W
0x0129 7:0 LUT9[7:0]
OSD_LUT9 (Default: 0 x 00) Look Up Table #9
R/W
0x012A 7:0 LUT10[7:0]
OSD_LUT10 (Default: 0 x 00) Look Up Table #10
R/W
0x012B 7:0 LUT11[7:0]
OSD_LUT11 (Default: 0 x 00) Look Up Table #11
R/W
0x012C 7:0 LUT12[7:0]
OSD_LUT12 (Default: 0 x 00) Look Up Table #12
R/W
0x012D 7:0 LUT13[7:0]
OSD_LUT13 (Default: 0 x 00) Look Up Table #13
R/W
0x012E 7:0 LUT14[7:0]
OSD_LUT14 (Default: 0 x 00) Look Up Table #14
R/W
0x012F 7:0 LUT15[7:0]
OSD_LUT15 (Default: 0 x 00) Look Up Table #15
R/W
84
DATASHEET
S5D4100X
6.8 BOOSTUP 0x0140 7:3 2:0 X1[10:8] Reserved Boost Up Calculation Area for Left Top Horizontal point BU_X1_MSB (Default: 0x 00) R/W
0x0141 7:0 X1[7:0]
BU_X1_LSB (Default: 0x 00) Boost Up Calculation Area for Left Top Horizontal point
R/W
0x0142 7:3 2:0 Y1[10:8] Reserved
BU_Y1_MSB (Default: 0x 00) Boost Up Calculation Area for Left Top Vertical point
R/W
0x0143 7:0 Y1[7:0]
BU_Y1_LSB (Default: 0x 00) Boost Up Calculation Area for Left Top Vertical point
R/W
0x0144 7:3 2:0 X2[10:8] Reserved
BU_X2_MSB (Default: 0x 02) Boost Up Calculation Area for Right Bottom Horizontal point
R/W
0x0145 7:0 X2[7:0]
BU_X2_LSB (Default: 0xD0) Boost Up Calculation Area for Right Bottom Horizontal point
R/W
0x0146 7:3 2:0 Y2[10:8] Reserved
BU_Y2_MSB (Default: 0x 00) Boost Up Calculation Area for Right Bottom Vertical point
R/W
0x0147 7:0 Y2[7:0]
BU_Y2_LSB (Default: 0x F0) Boost Up Calculation Area for Right Bottom Vertical point
R/W
0x0148 7 6:3 2:0 X3[10:8] DISP_AREA_SEL
BU_X3_MSB (Default: 0x 00) Boost Up Display Area Select 0: The value set in 0x0148 ~ 0x014F is applied to the display area. 1: The value set in 0x0140 ~ 0x0147 is applied to the display area. Reserved Boost Up Display Area for Left Top Horizontal point
R/W
85
DATASHEET
S5D4100X
0x0149 7:0 X3[7:0]
BU_X3_LSB (Default: 0x00) Boost Up Display Area for Left Top Horizontal point
R/W
0x014A 7:3 2:0 Y3[10:8] Reserved
BU_Y3_MSB (Default: 0x 00) Boost Up Display Area for Left Top Vertical point
R/W
0x014B 7:0 Y3[7:0]
BU_Y3_LSB (Default: 0x 00) Boost Up Display Area for Left Top Vertical point
R/W
0x014C 7:3 2:0 X4[10:8] Reserved
BU_X4_MSB (Default: 0x 02) Boost Up Display Area for Right Bottom Horizontal point
R/W
0x014D 7:0 X4[7:0]
BU_X4_LSB (Default: 0xD0) Boost Up Display Area for Right Bottom Horizontal point
R/W
0x014E 7:3 2:0 Y4[10:8] Reserved
BU_Y4_MSB (Default: 0x 00) Boost Up Display Area for Right Bottom Vertical point
R/W
0x014F 7:0 Y4[7:0]
BU_Y4_LSB (Default: 0x F0) Boost Up Display Area for Right Bottom Vertical point
R/W
86
DATASHEET
S5D4100X
0x0150 7 CAL_AREA_ON
BU_ACC (Default: 0x 10) The calculation area is indicated on the screen. 0: Calculation area indication OFF 1: Calculation area indication ON The display area is indicated on the screen. 0: Display area indication OFF 1: Display area indication ON The LUT graph is displayed on the screen. 0: LUT GRAPH OFF 1: LUT GRAPH ON Adaptive Contrast Control ON/OFF 0: OFF 1: ON Method of modifying Max value used in adaptive contrast control 0: 1/2 of the initially created Max value 1: 1/4 of the initially created Max value 2: 1/8 of the initially created Max value 3: 1/16 of the initially created Max value Method of modifying Min value used in adaptive contrast control 0: 1/2 of the initially created Min value 1: 1/4 of the initially created Min value 2: 1/8 of the initially created Min value 3: 1/16 of the initially created Min value
R/W
6
DISP_AREA_ON
5
GRAPH_ON
4
BU_ST_ON
3:2
Ymax_ctrl
1:0
Ymin_ctrl
0x0151 7 Ymax_num
BU_MAX_NUM (Default: 0x 80) Minimum pixels to be found with the MAX value
R/W
0x0152 7 Ymin_num
BU_MIN_NUM (Default: 0x 80) Minimum pixels to be found with the MIN value
R/W
0x0153 7:4 3:0 MAX_ALPHA MIN_ALPHA
BU_MAX_MIN_ALPHA (Default: 0x 44) Adaptive IIR Filter Gain for MAX value Adaptive IIR Filter Gain for MIN value
R/W
0x0154 7:0 TURN_POINT
BU_TURN_POINT (Default: 0x 00) Inflection point of the LUT ram graph
R/W
87
DATASHEET
S5D4100X
0x0155 7:0 BU_CORING
BU_CORING (Default: 0x 00) Adaptive Brightness Control Coring Value
R/W
0x0156 7:4 3:0 AVR_ALPHA BU_GAIN
BU_AVR_ALPHA_GAIN (Default: 0x 44) Adaptive IIR Filter Gain for Average value Adaptive Brightness Control Gain value
R/W
0x0157 2:0 DI_HTOTAL[10:8]
DI_HTOTAL_MSB Horizontal Input Total Pixel Value, Read Only
RO
0x0158 7:0 DI_HTOTAL[7:0]
DI_HTOTAL_LSB Horizontal Input Total Pixel Value, Read Only
RO
0x0159 2:0 DI_VTOTAL_ ODD [10:8]
DI_VTOTAL_ODD_MSB Vertical Input Total ODD Pixel Value, Read Only
RO
0x015A 7:0 DI_VTOTAL_ ODD [7:0]
DI_VTOTAL_ODD_LSB Vertical Input Total ODD Pixel Value, Read Only
RO
0x015B 2:0 DI_VTOTAL_ EVEN[10:8]
DI_VTOTAL_EVEN_MSB Vertical Input Total EVEN Pixel Value, Read Only
RO
0x015C 7:0 DI_VTOTAL_ EVEN[7:0]
DI_VTOTAL_EVEN_LSB Vertical Input Total EVEN Pixel Value, Read Only
RO
88
DATASHEET
S5D4100X
7. ELECTRICAL SPECIFICATION
7.1 ABSOLUTE MAXIMUM RATINGS Table 4. Absolute Maximum Ratings Characteristics DC Supply Voltage Symbol VDD 1.8V VDD 3.3V VDD DC Input Voltage VIN 3.3V input buffer 3.3V interface / 5V tolerant input buffer DC Output Voltage VOUT ILatch TSTG Plastic 1.8V output buffer 3.3V output buffer Latch Up Current Storage temperature 100 - 65 to 150 Rating 2.7 3.8 3.8 6.5 2.7 3.8 mA C Unit V
7.2 RECOMMENDED OPERATION CONDITIONS Table 5. Recommended Operating Conditions Characteristics DC Supply Voltage Symbol VDD 1.8V VDD 3.3V VDD DC Input Voltage VIN 3.3V input buffer 3.3V interface / 5V tolerant input buffer DC Output Voltage VOUT TA 1.8V output buffer 3.3V output buffer Operating Temperature Commercial Rating 1.8 0.15 3.3 0.3 3.3 0.3 3.0 ~ 5.25 1.8 0.15 3.3 0.3 0 to 70 C Unit V
89
DATASHEET
S5D4100X
7.3 DC ELECTRICAL CHARACTERISTICS Table 6. DC Electrical Characteristics at 3.3V VDD1 = 3.3V 0.3V, VDD2 = VDDA = 1.8V 0.15V, TA = 25C Item Digital Power 1 Supply Voltage Digital Power 2 Analog Power High Level Low Level Input Voltage VIH VIL IOH = -4mA IOH = -20mA IOL = 4mA IOL = 20mA Schmitt Trigger Positive-going threshold Negative-going threshold High Level Low Level Input buffer Input buffer with Pull-down Input buffer VT+ VTCMOS CMOS 0.8 -10 10 -33 60 10 10 600 2.4 2.4 0.4 0.4 2.0 VDD Symbol VDD1 VDD2 VDDA Condition Min. 3.0 1.65 1.65 2.0 0.8 Typ. 3.3 1.8 1.8 Max. 3.6 1.95 1.95 Unit V V V V V V V V V V V A A A A mW
Input Current
IIH IIL
IOZ Pd
VIN = VDD
10 -10 -10
VIN = VSS VOUT = VSS or VDD PCKO = 80MHz
Tri-state Output Leakage Current Power Consumption
90
DATASHEET
S5D4100X
7.4 AC ELECTRICAL CHARACTERISTICS 7.4.1 Video Input Timing Characteristics
TV (= 1 / FV) TVH VCK TVL
TSU YI0~7, CI0~7, HD, VD, FLD Valid Data
THD Valid Data Valid Data
Item Setup Time to VCK, input YI0~7, CI0~7, HD, VD, FLD Hold Time to VCK, input YI0~7, CI0~7, HD, VD, FLD Input Frequency Input High Duration Time Input Low Duration Time
Symbol TSU THD FV TVH TVL
Min. 2.0 2.0
Typ.
Max.
Units ns ns
27 3.0 3.0
MHz ns ns
91
DATASHEET
S5D4100X
7.4.2 Display Output Timing Characteristics
TD (= 1 / FD)
PCKO (PCKO_PHASE[2] = 0)
PCKO (PCKO_PHASE[2] = 1)
90% 10% Tr Tf TPD
TPD RO0~7, GO0~7, BO0~7, PHSO, PVSO, PDEN
Valid Data
Valid Data
Item Propagation Delay Time from PCKO, Output RO0~7, GO0~7, BO0~7, PHSO, PVSO, PDEN Frequency, Output Display Clock PCKO Duty Cycle, Output Display Clock PCKO Rise Time, Output Display Clock PCKO Fall Time, Output Display Clock PCKO
Symbol TPD FD Cduty Tr Tf
Min. -3
Typ. 0
Max. 3
Units ns
80 45 50 55 3 3
MHz % ns ns
92
DATASHEET
S5D4100X
8. PACKAGE DIMENSION
8.1 88-FBGA-0707
0.15 C A 7.00 B
7.00
0.15 C
C
0.50
0.50
13 12 11 10 9 8 7 6 5 4 3 2 1
#A1 INDEX MARK
A B C D E F G H J K L M N
0.15
0.50
0.50
88-0.30
1.2
0.15 0.05
M M
CAB C
93
DATASHEET
S5D4100X
8.2 80-TQFP-1212
14.00 0.20 12.00 0-7 0.09-0.20
14.00 0.20
12.00
80-TQFP-1212
#80
#1 0.50
0.17-0.27 0.08 MAX M 0.05-0.15 (1.25) 1.00 0.05 1.20 MAX
NOTE: Dimensions are in millimeters.
94
0.60 0.15

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